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| FL4SHK | for some reason it appears that a Verilog `task` synthesizes to its arguments being driven with 'x | 16:07 |
|---|---|---|
| FL4SHK | https://paste.ee/p/Vqveu | 16:13 |
| tpb | Title: Paste.ee - View paste Vqveu (at paste.ee) | 16:13 |
| FL4SHK | https://paste.ee/p/xIcpk | 16:18 |
| tpb | Title: Paste.ee - View paste xIcpk (at paste.ee) | 16:18 |
| FL4SHK | well, first I ran the first paste.ee link through `sv2v` by zachjs | 16:25 |
| FL4SHK | I suppose I can just use regular `function`s | 16:27 |
| FL4SHK | and have them return a `struct` data type | 16:27 |
| FL4SHK | yosys should be able to handle that since sv2v converts structs to vectors | 16:27 |
| tnt | hat is the sv2v output ? | 16:34 |
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| FL4SHK | tnt: yes | 19:26 |
| FL4SHK | wait | 19:26 |
| FL4SHK | no | 19:26 |
| FL4SHK | tnt: here's the output of sv2v: https://paste.ee/p/1mivU | 19:31 |
| tpb | Title: Paste.ee - View paste 1mivU (at paste.ee) | 19:31 |
| FL4SHK | hm, wait a minute | 19:31 |
| FL4SHK | yeah, looks like maybe yosys doesn't deal with tasks that well anyway... | 19:33 |
| FL4SHK | at least not with arguments | 19:38 |
| FL4SHK | is there a good way to invoke a yosys script from a makefile? | 20:07 |
| FL4SHK | for like, different multiple designs | 20:08 |
| FL4SHK | and can I provide arguments to a script? | 20:08 |
| FL4SHK | guess I could just have the makefile generate a script | 20:10 |
| tnt | Mmm, yeah looks like a bug. | 21:07 |
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