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| arkanoid | hello! I'm a newbie handling yosys for the first time. By reading the manual/docs I'm not fully understanding the difference between `synth` script and `prep` script. Would you please try to explain it to me in simple terms? | 02:47 |
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| Guest45 | Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 | 04:16 |
| Guest45 | ABC: ABC command line: "source <abc-temp-dir>/abc.script". | 04:16 |
| Guest45 | ABC: | 04:16 |
| Guest45 | ABC: + read_blif <abc-temp-dir>/input.blif | 04:16 |
| Guest45 | ABC: + read_lib -w /home/dgkim/library/asap7.lib | 04:16 |
| Guest45 | ABC: Parsing finished successfully. Parsing time = 0.42 sec | 04:16 |
| Guest45 | ABC: Library "asap7sc7p5t_AO_RVT_FF_nldm_211120" from "/home/dgkim/library/asap7.lib" has 42 cells (0 skipped: 0 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.50 sec | 04:16 |
| Guest45 | ABC: Memory = 82.29 MB. Time = 0.50 sec | 04:16 |
| Guest45 | ABC: Warnings: genlib library reader cannot detect the buffer gate. | 04:16 |
| Guest45 | ABC: Some parts of the supergate-based technology mapper may not work correctly. | 04:16 |
| Guest45 | ABC: Warnings: genlib library reader cannot detect the invertor gate. | 04:16 |
| Guest45 | ABC: Some parts of the supergate-based technology mapper may not work correctly. | 04:16 |
| Guest45 | ABC: Warnings: genlib library reader cannot detect the AND2, NAND2, OR2, and NOR2 gate. | 04:16 |
| Guest45 | ABC: Some parts of the supergate-based technology mapper may not work correctly. | 04:16 |
| Guest45 | ABC: + strash | 04:16 |
| Guest45 | ABC: + &get -n | 04:16 |
| Guest45 | ABC: + &fraig -x | 04:16 |
| Guest45 | ABC: + &put | 04:16 |
| Guest45 | how to solve it? | 04:16 |
| Guest45 | I have BUF, AND2,NAND2,etc.. in .lib | 04:17 |
| jevinskie[m] | <so-offish> "jevinskie: What are you using..." <- I was probably going to use IDA scripted from the command line and just have it decompile the whole binary to C and then run some regexes over the C. Binja would be good too but I don’t have a headless license. I don’t even want to look into what it takes to get ghidra to spit out a C file from the command line. | 05:22 |
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| lofty | arkanoid: `prep` is mostly for formal verification: simple, relatively straightforward transformations that don't majorly change the design | 07:59 |
| lofty | `synth` is for ASIC/FPGA synthesis; here things like technology mapping and such occur. | 08:00 |
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| arkanoid | lofty: thanks! | 10:40 |
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| kittennbfive | Hello! I have noticed that there is a "-full" flag for the "opt" pass, but it isn't used for synth_ecp5. I hacked https://github.com/YosysHQ/yosys/blob/master/techlibs/ecp5/synth_ecp5.cc#L286 replacing "opt" by "opt -full" and it seems to increase the maximum speed for my design by about 5-15MHz. Is this just luck or ... ? Is there a reason there isn't a -fullopt flag or similar for synth_ecp5? | 21:29 |
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| lofty | kittennbfive: I mean, `opt` gets called a lot of times. normally it's just used for cleanup though. | 23:23 |
| kittennbfive | The strange thing is that if i add -full to the other opt-passes the maximum frequency goes down... But this is not a scientific experiment, just some random fiddling around... | 23:28 |
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