Thursday, 2023-05-18

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|{amehello, why does this00:10
|{amemodule laspi(clk,leds);00:10
|{ame   input clk;00:10
|{ame   output [7:0] leds;00:10
|{ame   reg    [23:0] counter;00:10
|{ame   always @(posedge clk)00:10
|{ame     begin00:10
|{ame        counter<=counter+1;00:10
|{ame     end00:10
|{ame   assign leds[7:0]=counter[23:16];00:10
|{ameendmodule00:10
|{amegive the following warning?00:10
|{ameABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").00:10
|{ame(yosys compiled from git)00:11
so-offishI finally got a workstation in for all things FOSS FPGA00:21
so-offishSo happy.00:21
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jevinskie[m]<lofty> "It also helps if your toolchain..." <- Reminds me, I promised someone else this week I’d do an automatic decompilation of the Quartus binaries and spit out all the option names passed to calls to cfg_*00:47
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|{ameon ice40-hx8k, how do you enable pull ups?04:55
cr1901I think you have to instantiate an SB_IO directly, and enable the pullup parameter04:56
|{ameis it a block for each input pin?05:06
|{ameI verified this works http://joshhead.net/posts/icestorm-notes.html05:06
tpbTitle: Josh Headapohl (at joshhead.net)05:06
cr1901Yes, needs to be done for each pin that you want to enable the pullup05:15
|{amethank you!05:19
tntyou can also set -pullup yes in the PCF.06:15
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lofty|{ame: the ABC warning is harmless; ignore it07:32
lofty(the real answer is that Yosys hasn't passed any flops to ABC, but calls a sequential optimisation pass)07:33
|{ametnt: thanks,that worked08:02
|{amelofty: thank you08:03
lofty|{ame: which Yosys flow are you using, by the way?08:03
|{amegit version08:03
|{amewith a ice board08:04
|{ame Yosys 0.29+11 (git sha1 d82bae32b, gcc 11.3.0-1ubuntu1~22.04 -fPIC -Os)08:04
loftyYou should consider using `synth_ice40 -abc9`08:04
loftyMaybe with `-dff` as well08:04
|{ameI am now using yosys -p "read_verilog -noautowire $(SOURCES) " -p "synth_ice40 -blif $@"08:05
lofty|{ame: there's a more idiomatic way of doing that, but sure08:12
loftyYou should add `-abc9 -dff` to the `synth_ice40` call08:13
|{amewhat's the proper way? I just cobbled up a makefile, but I'd love to do things the proper way if there's one08:13
tntmore importantly the -blif output makes me think you still use arachne-pnr ?08:14
|{ameyes,I do08:14
|{ame arachne-pnr -d 8k -p $(CONSTRAINT) -P ct256 $< -o $@08:15
loftyYeah, no, you should use nextpnr 08:15
loftyarachne-pnr has been dead for years08:15
lofty|{ame: if you just pass source files on the command line, Yosys will default to calling `read` on those files 08:16
loftySo you can do `yosys -p "synth_ice40 -abc9 -dff -blif $@" $(SOURCES)`08:16
loftyBut yes, you should use nextpnr; it's so much faster, and it's also maintained08:17
|{amethanks guys,I switched to it, and, indeed, for one case in which arachne could not route, nextpnr worked without problems08:22
loftyIt's also a lot faster, isn't it? :P08:23
|{ameit is, no more route passes filling the compilation buffer!08:23
loftyI mean, nextpnr is still kind of noisy, but it's fine :p08:24
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Guest66hello how to remove assign sentence?11:30
Guest66How to eliminate "assign" after synthesis?11:42
Guest66How to eliminate "assign" after synthesis?12:27
xiretza[m]asking once is enough, if someone has an answer they'll tell you12:28
Guest66sorry12:32
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Guest669.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).13:13
Guest66ERROR: FF AsyncQueueSink.$auto$ff.cc:266:slice$652898 (type $_DFF_PP0_) cannot be legalized: dffs with async set or reset are not supported13:13
Guest66how to solve it?13:13
tntDon't use async FF ... it's not supported in whatever technology you're trying to use obviously.13:22
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so-offishjevinskie[m]: What are you using for decompilation and how do I find out more about that16:15
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