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| singham | Can an FPGA be designed on an FPGA? | 05:36 |
|---|---|---|
| whitequark | sure, people did that | 05:55 |
| singham | Where, who? | 05:58 |
| singham | Can you show me some projects? | 05:58 |
| whitequark | azonenberg ran an emulated cpld on an fpga | 06:17 |
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| bl0x_ | singham: that was exactly my idea. O.o | 07:41 |
| bl0x_ | That would allow for hardware independent partial reconfiguration. | 07:43 |
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| * singham was afk | 09:40 | |
| * singham is back now | 09:40 | |
| singham | Who azonenberg? | 09:41 |
| singham | So the core idea is to have the simplest hardware black replicating many times | 09:41 |
| singham | bl0x_: Can you simplify the term? :D | 09:42 |
| singham | *block | 09:51 |
| jn | partial reconfiguration is a feature that some FPGAs support: it means that part of the design is changed at runtime, without changing other parts | 09:55 |
| singham | whitequark: What's the project name? | 09:56 |
| jn | usually this is a very hardware-specific process. with a virtual or emulated FPGA inside a physical FPGA it can be implemented without knowing the details of the underlying hardware FPGA, thus "hardware independent partial reconfiguration" | 09:57 |
| singham | Are there any books for studying designs of current FPGAs and designing one? | 09:58 |
| Sarayan | honestly fpgas are rather proprietary, usually requiring reverse-engineering to do anything with them that's not "use the officiel development tool" | 10:31 |
| singham | Yes, but what books do those proprietary companies use? | 10:52 |
| tnt | Their internal docs about their previous generation of FPGA ... | 10:55 |
| singham | tnt: :P | 11:07 |
| singham | What books are used to design their first version of FPGA? | 11:08 |
| singham | This would come under VLSI right? | 11:10 |
| jn | there are different aspects to learn about. chip design in general, which is probably covered in several good books, on one hand. design of FPGAs, which can probably be derived from first principles, experimentation, and rumors, on the other hand | 11:14 |
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| singham | I made this array of size 768000 and it is taking a lot of time on yosys | 14:07 |
| singham | I believe I am doing something wrong | 14:07 |
| singham | Is this just a bit too high in length? for hx8k | 14:08 |
| tnt | Huh ... depends how you wrote it. | 14:19 |
| tnt | and also, is it 768000x1 ? or is thay 768000 of 8 bits or ... | 14:20 |
| singham | reg [0:767999] foo; | 14:21 |
| singham | 1 bit | 14:21 |
| tnt | And how do you access it ? | 14:21 |
| singham | I push foo[0:7] | 14:22 |
| singham | copy it to bar and use that shift register | 14:22 |
| singham | bar = foo[0:7]; | 14:22 |
| singham | It is right syntactically, yeah? | 14:24 |
| singham | Since half an hour I wasn't able to get compiled with yosys | 14:24 |
| singham | Creating decoders for process `\foo.$proc$foo.v:80$394'. | 14:25 |
| singham | 4/8: $5\bar[767999:0] | 14:25 |
| singham | That 4th step takes forever | 14:25 |
| singham | How much maximum length have you used? | 14:26 |
| tnt | paste you code ... | 14:43 |
| tnt | but if it can't be mapped to a RAM block then the HX8k only has about 8k FFs ... | 14:43 |
| singham | It is very long. That pretty much is the issue. Length and initialization | 14:49 |
| tnt | _you_ should know if it's mappable to a ram, you're the designer, knowing what hardware you want built is your job. If it can't and must use FF, then I'm not sure how you're expecting to cram 770k FFs in a device that has 8k of them ... | 14:54 |
| singham | Alright, I'll correct it. I found that one person had used about 100k bits so I thought this should work | 14:56 |
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| singham | It is 128k bits | 15:36 |
| singham | Understood | 15:36 |
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| so-offish | ERROR: cell type 'TRELLIS_SLICE' is unsupported (instantiated as 'SLICE1') | 23:10 |
| so-offish | Just built from HEAD and I'm seeing this now | 23:10 |
| so-offish | I was using TRELLIS_SLICE to ensure the packer did what I wanted, and that appeared to be working for me | 23:11 |
| so-offish | Is this right? I should be able to use it as a primitive. | 23:11 |
| so-offish | Maybe it got renamed or something? | 23:12 |
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| bentomo | Would yosys be suitable as both a vhdl and <system>verilog parser only? I'm looking to develop a build plugin for the pantsbuild system. I'm wondering if yosys could serve as a backbone for just parsing files in a file system to search for things like instantiations and port connections. It looks like maybe there's a development version of yosys | 23:56 |
| bentomo | with VHDL support according to the documentation that's private. This would be for business use though and I don't think I couldn't get my company to use something that isn't open source. | 23:56 |
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