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| singham | Is there a list of non-synthesizable features of Verilog for yosys, nextpnr somewhere? | 08:41 |
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| singham | Anyone? | 10:36 |
| singham | I ask because in simulation, I'm getting the right results | 10:36 |
| singham | But flashing on my iCE40 board, I get nothing | 10:37 |
| singham | If you've faced such issues, any help will be appreciated | 10:37 |
| tnt | You will get warning for anything that's non-synthesizable. | 10:42 |
| tnt | However sim mismatches are a MUCH wider set than non-synthesizable ... | 10:43 |
| tnt | Post your code somewhere ... | 10:44 |
| singham | It's big | 10:45 |
| singham | How can I see sim mismatches? | 10:45 |
| tnt | Well then hire someone ... but there is no way we can give you a full digital design course over IRC ... | 10:45 |
| singham | I mean in verilog there is synthesizable code right | 10:46 |
| singham | So as long as I write synthesizable verilog, sim should equate synth right? | 10:46 |
| singham | I have done a course on digital electronics, and a course on verilog from IIT KGP on hardware modelling | 10:48 |
| jix_ | singham: there's IEEE 1364.1 which defines some synthesizable verilog, but it's much more conservative than what's used in practice and there's no equivalent for systemverilog AFAIK, but even for that restrictive subset there are sim mismatches | 10:49 |
| singham | The paper is paid | 10:50 |
| singham | Is there a list of accepted verilog keywords in yosys | 10:51 |
| tnt | synthesizable != deterministic you can write verilog that's synthesizable but that has behaviors "left to the implementation" and so the sim and synthesis tool are free to take different choices. | 10:52 |
| tnt | And that's excluding all the "real world" things that can change real behavior from sim ( unstable clock / hw limitations / any "external device and IO timings / real world delays / ... ) | 10:54 |
| singham | Yes, but the net effect should be same right?! | 10:57 |
| singham | Lowering clock frequency should get rid of those issues, shouldn't it? | 10:57 |
| jix_ | even _excluding_ all that, you still can have synthesizable verilog with sim mismatches | 10:59 |
| jix_ | if you suspect the issue actually is such a mismatch, you can try to see if you can reproduce the issue with a post synth simulation | 11:00 |
| singham | I think, then, those are the issues with simulation and synthesis tools | 11:00 |
| singham | Any HDLs should go towards perfect simulation and reasonably good synthesis such that final logic is delivered. | 11:01 |
| jix_ | it's an issue of verilog itself really, if you follow the standards you can still get mismatches for perfectly valid verilog | 11:01 |
| singham | if there's an if else statement within always block, does it need begin end | 11:01 |
| singham | always @(posedge clk) if foo this; else that; | 11:02 |
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| singham | Is this syntactically correct or | 11:02 |
| singham | always @(posedge clk) begin if foo this; else that; end | 11:02 |
| singham | Above format is needed? | 11:02 |
| tnt | If it was not syntactically correct, it wouldn't have built. | 11:03 |
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| jix_ | singham: If you're looking for help, I'd really recommend you try to reproduce the issue with a design that you are willing to share. | 11:04 |
| singham | tnt: Alright | 11:07 |
| singham | It is over 7 files. | 11:08 |
| singham | How can I share it? | 11:08 |
| jix_ | upload it somewhere public (e.g. github or a pastebin) and share a link | 11:11 |
| singham | https://gitlab.com/x653/xv6-riscv-fpga | 11:14 |
| tpb | Title: Michael Schröder / xv6-riscv-fpga · GitLab (at gitlab.com) | 11:14 |
| jix_ | so this is not your own code? given that this was developed using yosys and seems to be working fine for the author, I'm fairly confident that the issue has nothing to do with what yosys and nextpnr are doing | 11:22 |
| singham | That is the assumption, but since I was unable to reproduce it on my board, I'm trying to debug it. | 11:35 |
| singham | You see, I'm on the 4th stage of what you're suggesting | 11:35 |
| singham | jix_ and tnt Thanks folks. I will leave for now. | 11:40 |
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| tnt | Is there an attribute to prevent yosys from recoding a FSM ? | 14:57 |
| jix | tnt: untested, just from looking at the source: (* fsm_encoding = "none" *) | 14:59 |
| tnt | jix: tx ! | 15:00 |
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| so-offish | Sup ya'll | 18:25 |
| corecode | y'all* | 20:33 |
| so-offish | Sup y'all* ty | 20:53 |
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| bl0x | Sup all y'all o/ | 22:05 |
| so-offish | hi! | 22:11 |
| so-offish | Ok, I can officially crash nextpnr reliably. I am willing to go build it from source and turn on all debug options - is there a certain build option that would provide a log for the devs or anything? (nextpnr-ecp5) | 22:12 |
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