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| whitequark | tnt: having seen code by chipmunks i have to disagree :D | 07:32 |
|---|---|---|
| whitequark | care little enough and not even an US+ will save you... | 07:33 |
| tnt | whitequark: Ah, I guess you have seen "better" chipmunks and I'll have to defer to your expertise in the matter then :D | 07:59 |
| mewt | experience of those chipmunks sounds disquieting | 08:17 |
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| RowanG[m] | I have a top entity that is generic because I want to use it on multiple board revision that are all the same save for a different ram chip that has differing number of banks. | 17:00 |
| RowanG[m] | So I have a parameter on the top level module that specifies how wide the banks are | 17:01 |
| RowanG[m] | I can read the verilog fine from yosys but I'd like to set this parameter before doing anything else | 17:01 |
| RowanG[m] | But I can't seem to do it. | 17:01 |
| RowanG[m] | So I call yosys with the verilog file. | 17:02 |
| RowanG[m] | And see this in the prompt:... (full message at <https://libera.ems.host/_matrix/media/r0/download/libera.chat/3e1eaed25357b147919f08a682125391c3bf7dee>) | 17:02 |
| RowanG[m] | and do `setparam -set BANK_WIDTH 10 $abstract\Wrapper` | 17:03 |
| RowanG[m] | which doesn't complain | 17:03 |
| RowanG[m] | but when I then continue the default size of the parameter hasn't changed | 17:03 |
| RowanG[m] | is there some other way I can do this? | 17:03 |
| RowanG[m] | I tried to do it with defines but this doesn't work for some reason | 17:34 |
| * RowanG[m] sent a code block: https://libera.ems.host/_matrix/media/r0/download/libera.chat/a9f481c3eb6e0bb691ba5610325ed1fef0d00ebc | 17:34 | |
| RowanG[m] | This fails with: `./wrapper.v:17: ERROR: Failed to detect width for parameter \BANK_WIDTH!` | 17:34 |
| RowanG[m] | ooof this works I just missed the backtick... | 17:36 |
| gatecat | RowanG: try doing `hierarchy -top Wrapper -chparam BANK_WIDTH 10` after reading verilog but before doing anything else | 18:00 |
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| RowanG[m] | @gatecat thx :) | 19:43 |
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