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| tnt | What was the name of the plugin that was supposed to add full systemverilog support to yosys ? (not the paid one, the oss one) | 06:56 |
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| gatecat | tnt: uhdm and surelog? | 07:02 |
| tnt | gatecat: Ah yeah, thanks ! | 07:03 |
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| stephe | What’s a good dev board | 17:37 |
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| gatecat | stephe: what are you planning on using it for? | 18:33 |
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| stephe | gatecat: just learning | 19:02 |
| gatecat | stephe: https://1bitsquared.com/products/icebreaker ? | 19:02 |
| tpb | Title: 1BitSquared - iCEBreaker FPGA (at 1bitsquared.com) | 19:02 |
| mewt | fabric speed is the main basic issue you'd run into with UP5k, I guess? | 19:04 |
| tnt | IMHO while learning it's a good thing. You can code like a chipmunk and get stuff to fit and meet timing on a USP ... small and slow forces you to do things properly and build good habits. | 19:05 |
| mewt | Certainly can't disagree, just wanted to give explicit warning :D | 19:09 |
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