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| tnt | [Matt]: Mmm, 2 is definitely genclk on up5k and also according to the simulation model. | 04:36 |
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| [Matt] | tnt: I get Fout/4 when I use 10, Fout/1 using 00 :) (My thinking was that 10 is selecting the shiftreg divider output instead; setting bit 21 should've had no effect but further divided the clock (would need to recreate to verify whether it's /7) | 09:12 |
| [Matt] | tnt: IIUC shiftreg config shouldn't have no effect when using GENCLK? (A clue that 10 != GENCLK on this part :/ ) | 09:13 |
| tnt | Yes, but I find that suspitious because that would mean both that (1) they changed that part for the up5k and (2) their sim model doesn't match silicon. And that's rather unexpected, so I'd like a second confirmation to make sure that's the case. | 09:32 |
| [Matt] | For sure, something def. suspicious. I couldn't find any OSHW examples of its use, I'm happy to grab/test/report a known-working example... | 10:03 |
| [Matt] | Just providing my observations that plloutXSel=10 gives f/4 and =00 gives f/1! :) | 10:04 |
| [Matt] | (ICE40HX4K-TQ144 FWIW) | 10:04 |
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