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| [Matt] | Howdy all! I don't suppose anyone has tried dynamic reconfig. of iCE40 SB_PLL40_CORE on a HX part? (I noticed DR mentioned on the icestorm wiki, but seems to have no effect on HX4K, am likely holding it wrong..) | 16:00 |
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| tnt | I only tried it on UP5k ... but I don't see why it wouldn't work on HX. | 17:21 |
| tnt | Did you set TEST_MODE on the PLL ? | 17:22 |
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| [Matt] | tnt: I did not, is that required? (-> will try it, thx) | 22:34 |
| [Matt] | I feared TEST_MODE would lead to explosions or weird undef stuff | 22:34 |
| [Matt] | tnt: Aha! Many thanks, that helps (though the output is /4 from the programmed value, something's shifted :/ ) The wiki has a discrepancy, "25 bits, or 26 bits for the UP5k" followed by a 26/27b list, am I reading that right? | 23:22 |
| [Matt] | tnt: Got it working; seems 0=genclk for plloutXSel (not 2). (Using 2 as per wiki I noticed [21] affected output rate which IIUC it shouldn't, indicates SHIFTREG was being used.) Do you have perms to update the wiki to mention this (and TEST_MODE, and s/25/26/)? Thanks 1E6 for the mode hint! | 23:55 |
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