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josuah | wow, wow, wow, hang-on! | 17:02 |
---|---|---|
josuah | all suddenly, yosys asks me if I have been adopted | 17:02 |
josuah | is it something every hardware developer run through? | 17:03 |
josuah | it seems like one of these corner stone in circuit design is k-induction for verifying designs | 17:04 |
josuah | and a frequent problem ran into is: how do I enforce a "reset" to happen in the proof | 17:06 |
josuah | I can imagine "if (i_reset) reset_done <= 1;", and then "assume(i_reset || reset_done);" | 17:06 |
josuah | but what if at system startup, "reset_done = 1" and "i_reset = 0"? then "i_reset" never becomes 1 | 17:07 |
josuah | whichever "reset_done" variable that states "now I am initialised, you can carry on"... | 17:10 |
josuah | it might be fooled by having the system initialise directly with "yes, I'm sure now" == 1 | 17:12 |
josuah | likewise, one could imagine: "I remember my parents taking care of me as a child" (akin to "reset_done = 1") | 17:13 |
josuah | there could have been another past I do not remember with "different parents taking care of me" (akin to system that started at "reset_done = 1" but "i_reset = 0") | 17:16 |
josuah | trying to find some "early verification point" is the common challenge to both "have I been adopted" and "have the system been reseted" | 17:18 |
josuah | so maybe if I can solve "have I been adopted" I can manage to make SymbiYosys behave as I wish (verify! verify! verify!) | 17:19 |
* josuah imagines researchers constantly walking from the faculty of science to faculty of philosophy to find an answer to their math/IT questions :P | 17:21 | |
josuah | "asks my mother, she knows for sure"? | 17:28 |
josuah | well that would work: ask the mother*board* to issue a i_reset signal, like it can be done on FPGA, iirc with a reset signal issued early | 17:29 |
josuah | but not for verification: no hardware there | 17:29 |
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josuah | assert() -> cover() | 17:49 |
josuah | assume() -> what_i_need() | 17:49 |
josuah | "I do not know whether I was adopted, but it certainly does not look like so to me" | 17:55 |
josuah | "I do not know whether a reset did happen, but all variables look like being at '0'" | 17:56 |
josuah | `assume({ state, tx_shift_reg, tx_counter, o_wb_ack } == 0 || state > 0); | 17:56 |
josuah | heh, I'll figure out :) | 17:56 |
josuah | ^ skip this monologue unless you are bored :) | 17:57 |
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qball | :grin: | 18:45 |
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