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| davedavenport[i] | We running into some issues with sby, it seems error messages use non-existing variable: https://github.com/YosysHQ/sby/issues/152 we hit more of these. | 10:19 |
|---|---|---|
| davedavenport[i] | after fixing we also notice the latest sby does not works against https://github.com/ZipCPU/wb2axip anymore (but not directly clear to us why). | 10:20 |
| davedavenport[i] | older version ( 2 years ago) works. | 10:21 |
| davedavenport[i] | https://github.com/YosysHQ/sby/issues/153 | 10:43 |
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| jix | davedavenport[i]: should be fixed on master now | 14:38 |
| davedavenport[i] | thanks | 14:39 |
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| rowang077[m] | Hello everyone | 15:35 |
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| rowang077[m] | i have 2 clocks coming from the same PLL one is 50Mhz and the other 150Mhz. Their phases are identical. And I need to transmit data from the 150Mhz domain to the 50Mhz domain. Is it possible to write to one of the registers in the 150Mhz domain and then once every 3 cycles write those 3 registers to one register in the 50Mhz domain? | 15:38 |
| rowang077[m] | I would think since the phases are the same and the clock is a clean multiple this will work without metastability | 15:38 |
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| gordonDrogon | Hi. first time FPGA user here (old programmer/'trad. hardware" person) and I am very likely out of my depth here, trying to get PicoRV32 going on a Gowin FPGA (Tang Nano 9K board). I have 'larson scanner' going so-far using the Gowin IDE. Gowin supply a picorv system and I have loaded that up - and it works, but I want to take it apart to better understand the process. Gowin supply it all as encrypted binary blob - weird when it's all open sou | 17:03 |
| gordonDrogon | rce. I think I need the RV core, 'wishbone', some peripherals and the memory interface. gowin only seem to give it 32KB of RAM but the FPGA has 2MB of RAM. So... Is this a place where someone can point me at some documentation, or some 'bootstrap my brain' online documents to help or am I just biting off too much to start with? | 17:03 |
| gatecat | if you want Gowin specific stuff, I'll ping pepijndevos[m] (you might also want to join #yosys-apicula). unfortunately it's hard to think of some good resources off the top of my head but you might want to look at picosoc, which is an open source picorv32 SoC - the examples are for iCE40 but could easily be ported to Gowin | 17:42 |
| gatecat | most of that 2MB is internal SDRAM I believe which would need a controller (or perhaps PSRAM, I can't remember the various parts). the 32KB is probably just using the block RAM in the FPGA fabric rather than that. | 17:43 |
| gordonDrogon | gatecat, thanks. looking at picosoc now - just using gowin hardware, don't care about the tools, etc. | 17:55 |
| gordonDrogon | the gowin stuff looked promising at the time... | 17:55 |
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