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| lkcl | agg: sorry just caught up with what you wrote, yes, the address/data lines are shifted over, in a bizarre fashion. | 09:20 |
|---|---|---|
| lkcl | tim pearson from raptor engineering worked it out, last year | 09:21 |
| lkcl | https://git.libre-soc.org/?p=microwatt.git;a=blob;f=aquila/lpc_slave.v;h=828bacb0eddd3838870eda1bf4e1d008bc53bdad;hb=b2059937f5a4d9087f8d6b83dcdebc276e0a25dc#l2112 | 09:21 |
| tpb | Title: git.libre-soc.org Git - microwatt.git/blob - aquila/lpc_slave.v (at git.libre-soc.org) | 09:21 |
| lkcl | 2112 // The ECP5 block RAMs operate in a non-intuitive manner. | 09:21 |
| lkcl | 2113 // To connect both ports to the same set of memory cells, one port has to be attached | 09:21 |
| lkcl | 2114 // 1:1 in address and data lines, while the other is offset (data + 18, address + 5). | 09:21 |
| lkcl | pasting that so it ends up in the irc logs for anyone else to find in future when searching for this same issue | 09:22 |
| agg | lkcl: thanks for the link, I think that's only for the slightly weird PDPW16KD primitive that exposes the 36-bit-wide ports, not the regular DP16KD which doesn't have that shift in address lines (but does have four byte-enables in the four LS bits, so 14 address bits per port) | 11:19 |
| lkcl | agg: ahh. | 12:56 |
| lkcl | "slightly" weird lol | 12:56 |
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