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| machinehum | tnt: Why is usb3 so impossible? Not enough logic cells? | 05:00 |
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| machinehum | tnt: From googleing around I've found a bunch of your stuff. no3usb looks really interesting, what would be the limitations of getting it to work with HS? | 05:22 |
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| ikskuh | what's the verilog equivalent to a VHDL procedure? | 19:36 |
| ikskuh | i've searched a bit but tasks aren't meant to be used in synthesis? | 19:37 |
| gatecat | I'm pretty sure Yosys can synthesise tasks | 19:40 |
| gatecat | it can definitely synthesise functions | 19:40 |
| ikskuh | okay, cool. i'll try! | 19:40 |
| ikskuh | it's definitly easier to handle recurring tasks with it | 19:40 |
| ikskuh | is there something like enums? | 19:42 |
| ikskuh | or do i just create a huge amount of localparam ? | 19:42 |
| gatecat | enums should be supported in systemverilog mode (`read -sv`/`read_verilog -sv`, or automatic with a .sv extension and files passed on the command line) | 19:43 |
| ikskuh | i think iverilog doesn't like sv :( | 19:44 |
| lambda | are you sure you don't want to just use VHDL? :p | 19:44 |
| ikskuh | looks like verilog is more widespread | 19:45 |
| ikskuh | and i have more fun with verilog, but also like strict typing | 19:45 |
| ikskuh | it's also very satisfying to remove bits from your design as they are unnecessary | 19:55 |
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| killjoy | It looked to me that iverilog can use sv if you specify -g2012 to it. | 21:20 |
| killjoy | But I haven't tested this, it's just what the googles says. | 21:20 |
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