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| lambda | ikskuh: very pretty! | 09:52 |
|---|---|---|
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| ikskuh | thanks :) | 09:53 |
| ikskuh | the cool part is yet to come | 09:53 |
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| machinehum | Hello | 21:19 |
| ikskuh | heya o/ | 21:22 |
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| chaoticryptidz | hewwo | 21:31 |
| machinehum | Anyone have an idea as to the feasibility to a USB3 memory controller on iCE40-HX8K? Like something you would find on a USB flash drive? | 21:45 |
| machinehum | Or possibly USB2, I think that's a little more reasonable | 21:45 |
| tnt | USB3 ... not going to happen. | 21:49 |
| tnt | USB2, I don't see any major issues, you're going to need an external PHY for the USB2 High-speed, but implementing some basic usb storage backed by flash seems very doable. | 21:50 |
| ikskuh | yeah, i'd say the same | 21:54 |
| ikskuh | hm, i wonder if it is possible to create raw DVI signals with the ECP5 | 21:59 |
| ikskuh | if my calculations are correct, i'd need to emit data with 400 MHz | 22:00 |
| ikskuh | (for 40 MHz pixel clock) | 22:00 |
| tnt | yes. It's been done. | 22:01 |
| ikskuh | uuuh | 22:02 |
| ikskuh | crazy | 22:02 |
| ikskuh | i wanted to use a TFP410PAP for this | 22:02 |
| tnt | Not really. It's not 400 MHz, it's 400 Mbps, so with DDR output it's really only "200 MHz". | 22:03 |
| ikskuh | i have 30 bit per pixel | 22:03 |
| ikskuh | in 3 channels | 22:03 |
| ikskuh | so 10 bits per pixel clock | 22:03 |
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| tnt | yes, but the io register can output on both rising and falling edge of the internal clock. | 22:04 |
| ikskuh | oh | 22:05 |
| ikskuh | i'm a newbie, so i'm still learning things | 22:05 |
| ikskuh | is it legal to run a process with always @ (posedge clk, negedge clk) ? | 22:06 |
| tnt | No | 22:07 |
| tnt | (well .. not if you want it to be synthesizable at least) | 22:07 |
| ikskuh | so how can i do DDR then? | 22:07 |
| tnt | You need to instanciate black boxes blocks that represent the specific ECP5 hardware IO register. | 22:08 |
| ikskuh | ah | 22:08 |
| tnt | ODDRX1F for instance | 22:08 |
| ikskuh | what exactly is that? | 22:12 |
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