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| whitequark | it's unfortunately not a submodule | 05:54 |
|---|---|---|
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| cr1901_ | gatecat: Made changes to PR and rebased, should be good to go: https://github.com/YosysHQ/nextpnr/pull/858 | 22:26 |
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| Guest10 | couple of questions about creating rules files for memory_bram | 23:13 |
| Guest10 | is it possible to define the enable for a port as active low? or is that done during techmap? | 23:13 |
| Guest10 | how do I define multiple enables for a bram instantiation? I'm trying to at least partially generate nets for use in PCB layout and the last issue I'm having is with RAM/ROM...the device I'm mapping to has an OE, CE, and WE (when it's a ram)... | 23:15 |
| Guest10 | again, is that during techmap? Or do I need to explicitly create an instantiation in verilog for the ram instead of using logic [7:0] rom[2**13] | 23:16 |
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