Wednesday, 2021-12-15

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mshhas anyone looked at somehow combining packing and placing in nextpnr? experimenting here I see a fmax speedup (at a cost of slices) if I remove the FF packing in pack_remaining_luts. I assume some packed FFs are useful but some harm timing - after placing it'd be known. this is ecp511:05
loftymsh: you want to do exactly the opposite, really11:09
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gatecatmsh: it's complicated; newer arches tend to place the two seperately but that doesn't always help matters11:20
gatecatI had a go doing this for ECP5 a year or two ago and it didn't really help overall11:20
SarayanTheoretically you can jointly optimize the cost function (e.g. fmax) jointly, but I suspect the search space is insane11:21
Sarayan(remove jointly to taste)11:21
Sarayanit's probably a very fun and very complicated research field actually11:22
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Sarayanespecially since you're optimizing a max, and that's always a pain because you can change a lot of stuff without changing a max11:23
Sarayanand if you optimize a mean, or a mean square, you can end up with a very high max11:24
mshhm right. my thought was to try greedily unpacking paired ff/luts near yhe critical path11:24
mshlofty: what do you mean by opposite sorry?11:24
gatecatmsh: it's a big, PITA, patch but ultimately the fix would be to make FFs and LUTs separate bels like Nexus11:25
gatecatand then manipulating them seperately is much easier11:25
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loftyAnd like Mistral! :p11:25
Sarayanfwiw they seem to be separate in quartus11:25
loftyEffectively the placer decides the packing11:25
gatecate.g. you could do https://github.com/YosysHQ/nextpnr/pull/863 but only if criticality is less then some unit11:25
mshah *nod*11:26
gatecatmy predecessor's attempt at implementing the former part was https://github.com/YosysHQ/nextpnr/tree/dave/ecp5-split-bels and https://github.com/YosysHQ/prjtrellis/tree/split_slice11:28
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SarayanI know Micko is kinda afraid of the legal issues, but I dream of a llvm-of-fpga with yosys, nextpnr, mistral and its friends in one tree (you can add amaranth in there too, I wouldn't mind).  It would be nice for experimenting with the fundamental algorithms while having the simplicity of use of a software compiler (at least the good ones)11:30
loftyJust throw GHDL in there and now everything is GPL :P11:31
Sarayanwhat's ghdl?11:32
Sarayan(I wouldn't mind throwing an equivalent of gtkwave in there though)11:32
Sarayanghdl = vhdl frontend for that beast + cxxrtl?11:33
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loftySarayan: yeah12:14
mshgatecat: those patches are "working" but don't give a benefit?13:19
gatecatthey worked a couple of years ago13:19
msh*nod* thanks. I'll have a play around with them13:20
gatecathave fun!13:20
gatecatif they are at all promising then I'm happy to have a go at getting them back up to date13:21
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Sarayanhi, when I clean -dfx then do a make config-clang then make install, I'm getting a weird error:18:25
Sarayan[ 99%] Building abc/abc-f6fa2dd18:25
SarayanERROR: ABC contains local modifications! Set ABCREV=default in Yosys Makefile!18:25
Sarayanmake: *** [Makefile:745: abc/abc-f6fa2dd] Error 118:25
SarayanI'm in sync with origin/master18:26
Sarayanoh, it's a friggin' submodule18:27
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