Saturday, 2021-12-11

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pepijndevos[m]what is this...12:00
pepijndevos[m]```12:00
pepijndevos[m]Automatically selected $abstract\top as design top module.12:00
pepijndevos[m]```12:00
pepijndevos[m]Latest yosys master is picking the wrong top module12:01
pepijndevos[m]seems related to https://github.com/YosysHQ/yosys/pull/123312:05
pepijndevos[m]From what I understand it creates abstract modules, which should get resolved by hierarchy, which is also doing the auto-top part12:11
pepijndevos[m]So seems weird that it'd pick the abstract module?12:11
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pepijndevos[m]If I run with `-top top` it works fine btw12:43
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pepijndevos[m]using `read_verilog` also solves the problem12:54
pepijndevos[m]but it still seems like a regression12:54
pepijndevos[m]https://github.com/YosysHQ/yosys/issues/305512:56
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gatecatpepijndevos[m]: a deliberate regression, which is the best kind :D14:21
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gatecathttps://github.com/YosysHQ/yosys/pull/309914:21
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gatecatperhaps we should have some kind of error when abstract modules are found to tell people to run hierarchy or use -r14:22
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cr1901Move at a moderate pace and hopefully don't break things17:06
* lofty reads this, sees that nextpnr-mistral is broken and looks at the camera17:16
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