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| Guest65 | I built yosys 0.12 . I still can't clear the xilinx tests | 06:35 |
|---|---|---|
| Guest65 | the ones within tests/arch/xilinx | 06:35 |
| Guest65 | It shows error Makefile:808 Error 2 | 06:36 |
| Guest65 | https://notabug.org/sagaracharya/hyperbola_os/raw/master/yosys/PKGBUILD | 06:36 |
| Guest65 | If someone is on arch, one can uncomment check function on above link, execute makepkg and reproduce the error | 06:37 |
| Guest65 | Please help in case the error is not in the software itself. | 06:37 |
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| Guest656 | Does anyone know Andres Navarro? | 13:08 |
| Guest656 | Probably born in 82 | 13:08 |
| Guest656 | module clock_generator | 13:10 |
| Guest656 | (input clk, | 13:10 |
| Guest656 | output clk_vga, | 13:10 |
| Guest656 | output reset_vga | 13:10 |
| Guest656 | ); | 13:10 |
| Guest656 | I have this 3 parameter module which has been instantiated using 5 parameters. Is this valid? | 13:10 |
| Guest656 | clock_generator clock_generator(.clk(clk), | 13:14 |
| Guest656 | .clk_usb(clk_usb), | 13:14 |
| Guest656 | .reset_usb(reset_usb), | 13:14 |
| Guest656 | .clk_vga(clk_vga), | 13:14 |
| Guest656 | .reset_vga(reset_vga) | 13:14 |
| Guest656 | ); | 13:14 |
| Guest656 | Like this | 13:14 |
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| * cr1901 thinks the topic should mention that "IRC is async" and to "stick around for a few hours" | 14:58 | |
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