Monday, 2021-10-18

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sf-slack1<gergo> @pgielda @mithro I mean it's not like I'm doing much other than feeding one tool's output into the other's input :)02:36
sf-slack1<gergo> @mithro @pgielda https://github.com/SymbiFlow/symbiflow-arch-defs/issues/2307 is the one that is tripping me up for now. It'd be great to know at least if it's a SymbiFlow bug, or if Clash is generating shabby Verilog that happens to work with proprietary toolchains02:39
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tcalgatecat: I have a nexus design where router1 finishes (so we know it's a routable placement), but router2 gets into a livelock situation where two nets keep stealing the same segment from each other.  `bwd wire: X45/Y3/JD0 (curr 1 hist 2073.000000 share 1)`    If it's interesting to you I can send it.05:17
gatecattcal: yeah, I'm a bit busy with another commitment at the moment but solving this is on my near term todo list and the more cases the better so please do send it06:33
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mithro@gergo: It could be both :-P14:50
mithro@acomodi: Could you review https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1885? It would be good for someone from Antmicro to understand the Odin-II work.14:51
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netimaginghi, is this an english channel? 16:24
sf-slack1<kgugala> Yes16:25
netimagingOk, thanks. Without going so deep, we're developing a new product for a big customer for us. We are currently in the "product selection" process and we discover this new world of "open fpga's". is it worth the money in front a mcu and a rtos?16:31
netimagingThe MCUs that we are in the selection are:16:32
netimagingCortex-M33 and Cortes-M416:32
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