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| sf-slack1 | <gergo> OK I managed to reduce it into a single 34-line Verilog input that is mis-synthesized with SymbiFlow. Which repo's issue tracker would I report this to? | 10:51 |
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| sf-slack1 | <gergo> Unfortunately, I still can't run `fasm2bels` on it | 10:55 |
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| mithro | gatecat: https://ieeexplore.ieee.org/abstract/document/9556370 | 17:32 |
| tpb | Title: Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence | IEEE Conference Publication | IEEE Xplore (at ieeexplore.ieee.org) | 17:32 |
| mithro | @gergo -- Thanks for all your awesome work getting clash going with SymbiFlow | 17:32 |
| sf-slack1 | <pgielda> @mithro @gergo yes, this is pretty cool work! | 18:16 |
| mithro | gatecat: Also https://ieeexplore.ieee.org/abstract/document/9556493/ | 18:23 |
| tpb | Title: Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs | IEEE Conference Publication | IEEE Xplore (at ieeexplore.ieee.org) | 18:23 |
| gatecat | thanks for the papers, mithro! | 18:30 |
| mithro | I have a few alerts around VPR and nextpnr | 18:30 |
| mithro | Sadly I don't have the time to actually read and understand the papers it finds | 18:31 |
| mithro | So I try and route them to people who do :-) | 18:31 |
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