Wednesday, 2023-03-15

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MoeIcenowysomlo: so it looks like a proper H increases the size at ~50% ?02:01
MoeIcenowy(not properly calculated02:01
MoeIcenowysomlo: chipyard is https://github.com/ucb-bar/chipyard02:01
cr1901proper H?02:01
MoeIcenowycr1901: previously we didn't properly enable H because of some weirdness of Rocket02:02
cr1901I didn't even know "H" was an extension02:03
* cr1901 lost count02:03
MoeIcenowyHypervisor02:03
cr1901ahhhhh02:03
cr1901RISCV IMAFDCOMGWTFBBQ02:04
MoeIcenowycr1901: you are out of date02:05
cr1901Oh?02:05
MoeIcenowynow it's RV64IMAFDCVSUZicsrZifenceiSs1p1202:05
MoeIcenowylike this02:05
cr1901It's missing the L spec02:05
cr1901:P02:05
cr1901(Also, My God we've run of out alphabet, haven't we?)02:06
MoeIcenowynew single-letter extension now rarely appear02:06
MoeIcenowycr1901: yes02:06
MoeIcenowyand it tend to divide single letter ones to multiple multi letter ones02:06
MoeIcenowye.g. original B is now ZbaZbbZbs ...02:06
cr1901Well, L spec is Decimal Floating Point, which I'm actually curious about just because it would be interesting. But there hasn't been movement on it AFAIK02:06
cr1901ahhhh02:06
cr1901Is the single letter "B" still used if the entirity of  "ZbaZbbZb..." is implemented?02:07
MoeIcenowywell I dont know...02:08
MoeIcenowyWaterman says there's now no B extension02:09
MoeIcenowySiFive has some B option02:09
cr1901ahhh, I remember when Claire Wolf (yosys dev) was working on the B extension. Idk if she still is, but you're right that I'm out of date.02:09
MoeIcenowybut it does not even contain Zbs02:09
MoeIcenowyit's only ZbaZbb02:09
MoeIcenowycr1901: well in RV context maybe you should better call her picorv32 dev ;-)02:10
cr1901Hehehe fair enough :D!02:10
MoeIcenowyI do admire picorv32 and it inspired me when I was doing my homework in college on Computer Orgnization02:11
cr1901There was no RV when I took Comp Arch, so we made our own bare minimum RISC CPU in Verilog w/ custom insns.02:12
MoeIcenowy(well I did a very rubbish rv32i (even without Zicsr) core then, and did run something produced by GCC02:12
cr1901I have a RV32 core that's "mostly" ready, but I need to write the microcode for it (size optimized!). I'll get it merged into LiteX after that02:12
MoeIcenowyoh I want to see it ;-)02:13
MoeIcenowyI am always curious about microcoding, but I haven't really understood it02:13
MoeIcenowy_florent_: could main ram be used as DMA destination?02:14
MoeIcenowyGW2A-18 is not very rich of BRAM02:14
MoeIcenowybut I got the 8MB SDRAM on GW2AR-18C running02:14
cr1901MoeIcenowy: https://mastodon.social/@cr1901/109847259530300392 Re: microcode, "Bit-Slice Microprocessor Design" by Mick and Brick02:19
tpbTitle: William D. Jones: "For those who have no idea how microcoded CPUs wo…" - Mastodon (at mastodon.social)02:19
MoeIcenowysomlo: btw Zenithal says Zk* Zb* are heavy of size02:19
MoeIcenowyah thanks02:19
cr1901Like pico/femtorv32, my RV core isn't fast. It's meant to be small. Microcoding it is intended to abuse block RAMs as a way to use less FPGA logic02:22
MoeIcenowycr1901: or maybe it can use LUTRAM?02:27
cr1901Yes, that's also an option for non-ice40 FPGAs02:29
cr1901My scripts for testing size were meant for the worst case of ice40 (no LUTRAM)02:29
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MoeIcenowy_florent_: GW2A-18 seems to be very short on BRAM, when I use standard vexriscv + sdcard, I got `The number(49) of BSRAM in the design exceeds the resource limit(46) of current device.`03:06
MoeIcenowymaybe I should look at GowinSynthesis result03:09
somloAll I wish for is yosys/nextpnr for whatever FPGA is on the Alveo boards ;P03:38
somloif only I didn't have to work for a living, I could dedicate the next 10 years to making it happen :D03:39
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MoeIcenowywell litesdcard seems to use 18 BSRAMs07:13
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