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| cr1901 | somlo: Rocket is an out-of-order core, yes? Is it worth keeping FPU-less around for academic study (and to increase Fmax)? | 03:32 |
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| somlo | cr1901: good point; then, maybe, the way forward is to remove core count and mem-bus width from the variant *name*, and have them as additional parameters | 12:13 |
| somlo | each proper variant will have 1, 2, 4, or 8 cores, and be 1x, 2x, 4x, or 8x ( x 64 bit) mem bus width | 12:13 |
| somlo | I can still generate all of them from a couple of nested for loops in pythondata-cpu-rocket/.../verilog/... | 12:14 |
| somlo | but I guess what I find most annoying is the current variant naming scheme, which is in dire need of being cleaned up :) | 12:14 |
| somlo | cr1901: as for "out-of-order", that's not rocket -- you're probably thinking of BOOM (https://boom-core.org), which we don't (yet) have in LiteX | 12:49 |
| tpb | Title: RISC-V BOOM - RISC-V BOOM (at boom-core.org) | 12:49 |
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| Hongwei | Hello, I have a question for soc design. What's the version of wishbone bus? | 15:20 |
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| cr1901 | somlo: Yes, I was thinking of BOOM | 16:29 |
| cr1901 | For some reason I thought Rocket and BOOM were derived from the same underlying core | 16:29 |
| cr1901 | (but maybe they're just both written in Chisel) | 16:30 |
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| somlo | cr1901: BOOM is using rocket as a starting point (or building block, or something) | 19:32 |
| somlo | they talk about needing "chipyard" and deploying on amazon hosted FPGAs to play with it (which to me says it's HUGE, and one would have to be a Berkeley grad student under threat of not passing their qualifiers as an incentive to work through the entire learning curve of setting it up) :P | 19:33 |
| cr1901 | I have trouble reconciling two facts: 1. Out-of-order is complex, 2. It dates back to the 60s | 20:29 |
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