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MoeIcenowy | --with-pcie fails on Vivado 2022.2 for STLV7325 board | 06:59 |
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Guest9 | Hi, I would like to know if there is any documentation to understand how to generate RTL for the LiteDRAM. The current github page shows "Export Your Core SoC To Verilog" as a TODO. | 20:29 |
_florent_ | Guest9: LiteDRAM has a specific generator for this: https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py | 21:35 |
_florent_ | Guest9: you can find some configuration files here: https://github.com/enjoy-digital/litedram/tree/master/examples | 21:36 |
_florent_ | Guest9: Some examples of re-integration: | 21:36 |
_florent_ | https://github.com/antonblanchard/microwatt/tree/master/litedram | 21:37 |
_florent_ | https://github.com/chipsalliance/Cores-SweRVolf/tree/master/cores/litedram | 21:37 |
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