Tuesday, 2022-11-29

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sensillevery strange. when i generate a design with 0x2000 main_ram, the main ram does not work at all (data errors: 2048/2048). when i go into the generated .v and change the size to 1024, the first 1k works. when i set it to 1025, it's broken again09:23
sensillethe signals look ok in litescope. write cycle looks good to me, but the next read gives the old value09:24
sensille when i reduce integrated_sram to 0x1000 main_ram works with 0x200009:44
sensillegetting closer. main_ram size must be != sram_size10:38
sensilleINFO:Xst:3227 - The RAM <Mram_sram>, combined with <Mram_main_ram>, will be implemented as a BLOCK RAM, absorbing the following register(s): <sram_adr0>10:38
sensilleand indeed, main_ram content is equal to sram content (which is a copy of some rom content at 0)10:39
sensillei don't see from the generated .v why ISE thinks it can get away with using only one RAM instance for both sram and main_ram11:11
sensillebut i have my workaround for now11:18
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