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| F4PGASlackBridge | <kenneth.wilke> lkcl: Thanks for sharing, I appreciate hearing that personal perspective. My experience is mostly based on being a self taught Linux practitioner and software engineer, with attempts to branch out into hardware here and there. I had several attempts to learn HDL but the tooling was usually pretty overwhelming. I did finally start to gain some ground when I was playing with FPGAs and CAPI while working on the | 00:08 |
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| F4PGASlackBridge | OpenPOWER Barreleye servers at Rackspace and could ask my random noob questions to folks from IBM and Xilinx. Overall though I think it's safe to say I have barely a clue what I'm doing when it comes to hardware, but I'm stubborn enough to keep trying anyway! | 00:08 |
| F4PGASlackBridge | <kenneth.wilke> The wild west side of HDL certainly appeals to me though, with FPGAs having the appeal of running my janky designs in a much more ephemeral way. Though I would consider taking a crack at open source ASIC designs if my skills reach the point where that's a practical enough choice | 00:17 |
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| F4PGASlackBridge | <as85> @kenneth.wilke On top of that, wouldn't the cost of fabrication for ASIC designs be astronomical, even for low volume solutions? From what I understand (which is not very much) it seems like there are few options for getting ICs made, and even with older processes the costs seem to discourage smaller groups from experimenting. | 04:10 |
| F4PGASlackBridge | <kenneth.wilke> @as85 I share that same view, the only way it seems like it would be feasible for most small groups would be if your design makes it into the Multi-Project Wafer thing that Google sponsors: https://efabless.com/open_shuttle_program/ | 04:47 |
| tpb | Title: Open Source Shuttle MPW-5 | Efabless (at efabless.com) | 04:47 |
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| lkcl | kenneth: yes i'm a software engineer as well, who tinkered with 74 logic gates and also did A-Level maths when younger | 09:14 |
| lkcl | i couldn't "grok" HDL at all until i started consistently, persistently, and religiously looking at yosys "show top" diagrams after each and every single modification to the HDL | 09:15 |
| lkcl | for six months straight (!) | 09:15 |
| lkcl | like this: https://libre-soc.org/3d_gpu/priority_picker_16_yosys.png | 09:16 |
| lkcl | is the output from this: https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/picker.py;h=0babc074a9eeb9663793bcc4fd1bfdb259d631bc;hb=7a3ab7ecce390b2003ff61befca59cd4ad6b7428#l32 | 09:17 |
| tpb | Title: git.libre-soc.org Git - nmutil.git/blob - src/nmutil/picker.py (at git.libre-soc.org) | 09:17 |
| lkcl | the other thing: i very deliberately picked nmigen (which is Trademarked btw - and still an Open Source Project, like how Mozilla trademarks Firefox) *precisely* because i'm trained as a Software Engineer | 09:19 |
| lkcl | as85: sky130 google-sponsored designs, up to 10mm^2, are entirely free. no charge. no money. zip. nada. | 09:20 |
| lkcl | caveat: your entire design *must* be Open Source Licensed. | 09:20 |
| lkcl | efabless ChipIgnite is only USD 8.5k | 09:21 |
| lkcl | if you're thinking "holy crap that's expensive", you'd be dead wrong. any other MPW - if you can even get access to one these days - is 5 to 10x that price | 09:22 |
| lkcl | eFabless negotiated the price down by taking responsibility for many of the tasks normally covered (laboriously, manually) by the Foundry, and (surpriise) automating them, by applying intelligent Software Engineering / IT practices | 09:23 |
| lkcl | also, again, if you have an entirely Libre/Open VLSI design and use coriolis2, there is a Foundry in Japan that is i think 2 micron (200 nm, close to the usual 180nm) in a small town | 09:24 |
| lkcl | that is used for "training" of its employees. i can make an indirect introduction (point you in the right direction) and you won't have to pay for that, at all, either | 09:25 |
| lkcl | sorry, 2 micron is 2,000 nm. BIG :) | 10:03 |
| lkcl | i need to check on that | 10:03 |
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| F4PGASlackBridge | <as85> @ikcl I have no issues with open sourcing designs (I would do it anyway) but from my understanding the skywater program by Google requires your project to be selected, that is, there is no guarantee that your design will be made. Is the foundry in japan similar, or will they fabricate most reasonable designs? | 15:41 |
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| F4PGASlackBridge | <kenneth.wilke> @as85 I think I view this similarly as well. I'd prefer my designs to be open source to share with other tinkerers and maybe get useful feedback from more experienced engineers. I think you're correct that there is no guarantee of acceptance. Admittedly that does affect my willingness to spend personal time exploring that path but I still see it as a pretty awesome and generous opportunity. I really enjoy the | 18:14 |
| F4PGASlackBridge | idea of aspirational CompSci students or other tinkerers having that chance, but for now I'm focused on areas that I feel more confident could yield (pun intended) results for the kinds of projects I work on | 18:14 |
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| mithro | https://dl.acm.org/doi/abs/10.1145/3519599 - An Optimized GIB Routing Architecture with Bent Wires for FPGA -- The experimental results show that the GIB architecture with length-4 wires can achieve 9.5% improvement on the critical path delay and 11.1% improvement on the area-delay product compared to the VTR CB-SB architecture with length-4 wires. After exploring mixed wire types, the optimized GIB architecture can further improve the | 19:52 |
| mithro | delay by 16.4% and area-delay product by 17.1% compared to the CB-SB architecture with length-4 wires. | 19:52 |
| tpb | Title: An Optimized GIB Routing Architecture with Bent Wires for FPGA | ACM Transactions on Reconfigurable Technology and Systems (at dl.acm.org) | 19:52 |
| nimh | everyone seen this? https://pygears.org/ | 19:53 |
| mithro | There website is all new and fancy! | 19:59 |
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