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| F4PGASlackBridge | <kenneth.wilke> I'm curious what the scene looks like for open source IP blocks. I've known about OpenCores for quite a while and have come across the OpenFPGA IP generator and Libre Cores more recently, but my skills aren't developed enough to get any sense of the usefulness of any of these. Does anyone have any opinions or insights on these or other open source IP catalogs or building blocks? | 19:39 |
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| lkcl | kenneth: it's... an interesting inflection point. 20 years ago a small dedicated group started opencores and released a whole stack of RTL, Rudi from ASICs.ws, and Richard Herveille are two i've met who released silicon-proven HDL that could also be used on FPGAs | 23:21 |
| lkcl | but the FPGAs were slow, small, expensive and all ran proprietary toolchains. | 23:22 |
| lkcl | nobody really designed anything "significant" in the open source / open hardware world, because, well, it would only ever run at 1/10th of ASIC speeds | 23:23 |
| lkcl | now the brakes are off: you can buy FPGAs with 500k LUTs *and get a Libre toolchain for it* | 23:24 |
| lkcl | oh and you can put it into silicon at metally-low pricing (free via google-sponsored MPWs) | 23:25 |
| lkcl | so it's gone from "yeah why should be bother, Libre Silicon will never happen" to "holy cow this is awesome" in about 18 months flat | 23:26 |
| lkcl | the trickiest part though - one thing you have to watch out for - is the lack of a "pinmux" in the Libre/Open ASIC world | 23:28 |
| lkcl | FPGAs you just don't bother, i mean, why would you need to re-map multiple functions onto a limited set of pins, just recompile the bitstream, right? | 23:28 |
| lkcl | turns out that doing an auto-generated peripheral fabric that can map multiple cores in a reconfigureable way onto a limited number of IOpads is *hard* | 23:30 |
| lkcl | but not for reasons that are immediately obvious | 23:30 |
| lkcl | i wrote one for the Shakti Group, when i visited IIT Madras about 3 years ago. it was an auto-generator peripheral fabric, written in python, using Bluespec code-fragments | 23:31 |
| lkcl | 3 months work later, and it was capable of generating the FULL peripheral interconnect: AXI Bus Master, AXI Bus addressing, interrupt controller, connecting all IRQs to a PLIC, the works | 23:32 |
| lkcl | end result? | 23:32 |
| lkcl | absolutely awful unmaintainable unreadable code | 23:32 |
| lkcl | *five* levels deep of nested code-generation similar to Zope / Plone (if you remember that) | 23:33 |
| lkcl | the only other pinmux-aware peripheral-fabric-generator i know of, which was inspired by what i wrote, is Earl Grey, part of OpenTITAN, by the lowRISC team | 23:33 |
| lkcl | they used verilog templates embedded with python-jinja code-fragments, similar to PHP | 23:34 |
| lkcl | it's just as unreadable as what i wrote | 23:34 |
| lkcl | don't get me wrong: what they did is absolutely brilliant, i mean they even completed the goals i set for myself which was to auto-generated the device-tree files, auto-generate linux kernel headers | 23:35 |
| lkcl | auto-generate documentation, everything | 23:35 |
| lkcl | incredibly powerful... | 23:35 |
| lkcl | ... but *only* understandable and maintainable by the people who actually wrote it. | 23:35 |
| lkcl | and | 23:36 |
| lkcl | if you want a different core, say, a Power ISA core which uses a XICS Interrupt Controller, you're hosed | 23:36 |
| lkcl | because both Earl Grey and the Shakti peripheral-generator assume a RISC-V core and therefore only provide (auto-generate) the infrastructure for a RISC-V PLIC | 23:37 |
| lkcl | want an OR1200 interrupt controller? nope. MIPS? nope, sorry. | 23:37 |
| lkcl | so yeah, it's... an interesting inflection point, a bit like the Wild West of HDL :) | 23:38 |
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