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| mangelis | hi, i wonder if it's possible in yosys to force that certain inputs are not connected to same luts? | 20:02 |
|---|---|---|
| mangelis | i have module with 9 input bits, and it would help if i could force that only bits 0,1,2 or internal bits can be connected to a lut, then only 3,4,5 and internals etc | 20:05 |
| mangelis | i've tried to do group0 = input[0]+input[1]+input[2]; group1 = input[3]+input[4]+input[5]; ... result=group0+group1+group2; but the synthesis results are the same than if i have everything in one big expression | 20:08 |
| Lofty | mangelis: Why do you need this? The solution is to just instantiate LUTs directly, but this is a weird thing to want | 20:08 |
| mangelis | the hardware i'm using to run the design can't access all the inputs directly. i'll have to insert manual "buffer" luts if it's not possible with yosys to directly generate valid result | 20:15 |
| Lofty | And...what is the hardware you're using? | 20:17 |
| Lofty | mangelis: ^ | 20:17 |
| mangelis | amiga blitter | 20:19 |
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| Lofty | You, um, what. | 20:19 |
| mangelis | :p | 20:19 |
| Lofty | Why are you trying to synthesise a design for the Amiga blitter? | 20:19 |
| mangelis | i already have, several | 20:19 |
| knielsen | oh, nice, I spent a _lot_ of time understanding how to use the blitter back then ;-) | 20:19 |
| Sarayan | wasn't the copper a lot funkier? | 20:20 |
| * Lofty sighs | 20:20 | |
| Lofty | Okay, well | 20:20 |
| mangelis | ah, missed your question "why" | 20:20 |
| Lofty | I wrote a Yosys flow for 7400 logic, so I'm in no position to judge | 20:20 |
| Lofty | The long and short of it is that what you have here is not a LUT. | 20:21 |
| Lofty | Instead, you need to instruct ABC to produce something which maps to the blitter | 20:22 |
| Lofty | There are two ways of doing this | 20:22 |
| Sarayan | also "what is connected to a lut" is not something you're supposed to care about, It's like dictation the asm instructions to a compiler | 20:22 |
| Lofty | <Lofty> The long and short of it is that what you have here is not a LUT. | 20:23 |
| mangelis | well actually blitter is a 3-input 1-output lut | 20:23 |
| Lofty | ... | 20:24 |
| Lofty | Then why aren't you mapping to LUT3s? | 20:24 |
| mangelis | i am | 20:24 |
| Lofty | But, that achieves what you're asking for, no? | 20:25 |
| mangelis | well no, because i'm trying to implement game of life now, and it needs to calculate 8 neighbours | 20:26 |
| Lofty | But you can construct that out of LUT3s. | 20:27 |
| mangelis | so when blitter is executing it reads 3 words from memory, performs this 3-to-1 boolean operation to all bits and writes output. you can do shifts by delaying some of the inputs. that gives a way how to access cells on the left | 20:28 |
| Lofty | I don't think Yosys is the tool for this. | 20:29 |
| mangelis | but to access cells on the right, blitter has to be run in "descending" mode. so one can not combine those in one blit operation. hence my need to group the inputs | 20:29 |
| Lofty | You can write a postprocessing script to group the inputs | 20:29 |
| mangelis | i know it's not. but i was just wondering if there exists some way to force certain operations | 20:30 |
| Lofty | ABC's idea of a LUT is too abstract to achieve this | 20:30 |
| mangelis | hmm okay | 20:30 |
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| mangelis | i imagine what i'd want is that i could force that optimization wouldn't happen across certain bits | 20:31 |
| Lofty | Even more: you're attempting to enforce a strict ordering of bits | 20:32 |
| Lofty | That's a constraint not even expressible to ABC | 20:32 |
| mangelis | ah, on verilog side i see that reg "group0" has 2 bits, which are generated by the sum of three input bits and then group0 is used in other expression | 20:34 |
| mangelis | but i guess it's not possible then to force the group0's 2 bits to "always exist" | 20:36 |
| mangelis | i'm not at all familiar how the synthesis works under the hood, thanks for telling me this anyway :) | 20:37 |
| Lofty | Well, I wrote a LUT mapper, so I know a reasonable amount on the subject | 20:40 |
| Lofty | Could I port my own LUT mapper to achieve this? Probably, but it wouldn't necessarily be as good | 20:40 |
| mangelis | cool | 20:41 |
| Sarayan | In fact you want to use yosys to generate a blitter configuration? | 20:42 |
| mangelis | Sarayan: more like i was thinking if i could add some constraints to generate design that fits the hw better | 20:43 |
| Sarayan | fun :-) | 20:47 |
| mangelis | actually while in shower i realized that non-blocking assignments probably do just what i want | 21:19 |
| mangelis | hmm, doesn't seem to change the result of synthesis. is the non blocking assigment -> flipflop mapping done somewhere else than just generic synthesis? | 21:21 |
| Lofty | That mapping is the proc pass, which is called by synth | 21:23 |
| mangelis | ah it probably needs a clock, ie. doesn't work inside always @( * ) | 21:28 |
| mangelis | wow, it actually generates less luts and satifies the constraint i wanted :-)) | 21:32 |
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