| *** tpb has joined #yosys | 00:00 | |
| *** lf has joined #yosys | 00:16 | |
| *** lf_ has quit IRC | 00:16 | |
| atk | okay, looks like it's entirely isolated to ghdl | 00:28 |
|---|---|---|
| *** Jay_jayjay has joined #yosys | 00:30 | |
| *** Degi has quit IRC | 00:40 | |
| *** Degi has joined #yosys | 00:42 | |
| *** Jay_jayjay has quit IRC | 01:59 | |
| *** peepsalot has quit IRC | 03:50 | |
| *** Degi_ has joined #yosys | 04:25 | |
| *** peepsalot has joined #yosys | 04:26 | |
| *** Degi has quit IRC | 04:27 | |
| *** Degi_ is now known as Degi | 04:27 | |
| *** sorki has joined #yosys | 04:43 | |
| *** srk has quit IRC | 04:44 | |
| *** sorki is now known as srk | 04:44 | |
| *** jfcaron has quit IRC | 04:58 | |
| *** proteusguy has quit IRC | 06:02 | |
| *** proteusguy has joined #yosys | 06:04 | |
| *** philtor has quit IRC | 06:11 | |
| *** philtor has joined #yosys | 06:15 | |
| *** craigo has joined #yosys | 07:02 | |
| *** emeb_mac has quit IRC | 07:30 | |
| *** jakobwenzel has joined #yosys | 08:40 | |
| *** vidbina_ has joined #yosys | 08:50 | |
| *** jakobwenzel has quit IRC | 08:53 | |
| *** jakobwenzel has joined #yosys | 09:04 | |
| *** somlo has quit IRC | 09:04 | |
| *** _whitelogger has quit IRC | 09:36 | |
| *** _whitelogger has joined #yosys | 09:38 | |
| lambda | atk: instantiating foreign modules from GHDL is kinda tricky, yes | 10:49 |
| atk | lambda: should I just do it from verilog instead? | 10:53 |
| atk | No idea how to do that but I guess I will have to figure it out | 10:53 |
| lambda | atk: it should work correctly with recent-ish versions of ghdl/-yosys-plugin though | 10:53 |
| lambda | you are declaring it as a component and instantiating that, right? | 10:54 |
| atk | yes, but my version isn't the most recent | 10:54 |
| atk | I was hoping to get away with only a minor change to the version which comes with my distro but I guess I will repackage against the most recent | 10:54 |
| *** moony has quit IRC | 11:08 | |
| *** moony has joined #yosys | 11:13 | |
| *** jakobwenzel has quit IRC | 11:49 | |
| *** jakobwenzel has joined #yosys | 11:55 | |
| atk | okay, that fixed it | 12:33 |
| atk | thanks lambda | 12:33 |
| lambda | awesome :) | 12:33 |
| atk | next step PLL, shouldn't be that hard given this progress | 12:34 |
| lambda | feel free to copy this component https://gitlab.com/YARM-project/soc/-/blob/master/vhdl/system_clocks_xilinx.vhd#L23-71 | 12:38 |
| tpb | Title: vhdl/system_clocks_xilinx.vhd · master · YARM / soc · GitLab (at gitlab.com) | 12:38 |
| lambda | oh wait, you' | 12:38 |
| lambda | re on iCE40, aren't you - nevermind then | 12:38 |
| atk | wrong FPGA :P | 12:38 |
| atk | no worries, I will figure it out | 12:38 |
| *** somlo has joined #yosys | 12:41 | |
| *** Jay_jayjay has joined #yosys | 13:06 | |
| *** emeb has joined #yosys | 14:22 | |
| *** modwizcode has joined #yosys | 14:48 | |
| cr1901_modern | daveshah: Does ecpbram have any known bugs? | 15:05 |
| daveshah | I've never used it | 15:05 |
| cr1901_modern | Ahhh | 15:06 |
| daveshah | are you seeing something strange? | 15:06 |
| cr1901_modern | >Inconsistent word width at line 9 of build/orangecrab/gateware/mem.init! >> | 15:06 |
| cr1901_modern | Okay, so I zero-pad the mem.init | 15:07 |
| cr1901_modern | And that causes ecpbram to stop bitching | 15:07 |
| cr1901_modern | but I don't get a working config as output | 15:07 |
| emeb | ecpbram worked for me here -> https://github.com/emeb/orangecrab_simple_6502/blob/4abeb827a629e34ec99d75b7a1f55bb77aa043da/trellis/Makefile#L46 | 15:08 |
| cr1901_modern | emeb: Thanks, I must be doing something wrong then | 15:11 |
| cr1901_modern | screw it, starting over | 15:11 |
| cr1901_modern | Oh okay I think I see the problem... mem.init is getting eaten by litex | 15:14 |
| cr1901_modern | based on the command-line options I pass to it | 15:14 |
| cr1901_modern | and ecpbram doesn't warn if the random sequence isn't found | 15:14 |
| emeb | I haven't spent much time with litex, but this sounds familiar. | 15:15 |
| cr1901_modern | Okay now it's working | 15:27 |
| cr1901_modern | cool | 15:27 |
| emeb | what did you have to do to convince Litex to work? | 15:35 |
| *** emeb_mac has joined #yosys | 16:52 | |
| *** sorki has joined #yosys | 17:08 | |
| *** srk has quit IRC | 17:09 | |
| *** sorki is now known as srk | 17:11 | |
| *** kraiskil has joined #yosys | 17:11 | |
| *** peeps[zen] has joined #yosys | 18:01 | |
| *** peepsalot has quit IRC | 18:02 | |
| cr1901_modern | emeb: I needed to run the build_*.bat/sh manually | 18:42 |
| cr1901_modern | because running it from the script in litex w/o compiling first (which is what I want when I only want to build the bitstream) will overwrite mem.init with an empty file | 18:43 |
| *** jakobwenzel has quit IRC | 18:59 | |
| *** kraiskil has quit IRC | 19:07 | |
| *** kraiskil has joined #yosys | 19:10 | |
| *** Jay_jayjay has quit IRC | 19:26 | |
| *** Jay_jayjay has joined #yosys | 20:25 | |
| *** vidbina_ has quit IRC | 21:25 | |
| *** maartenBE has quit IRC | 21:38 | |
| *** maartenBE has joined #yosys | 21:45 | |
| *** Thorn has quit IRC | 21:47 | |
| *** FFY00 has quit IRC | 21:52 | |
| *** FFY00 has joined #yosys | 21:53 | |
| *** kraiskil has quit IRC | 22:01 | |
| *** jfcaron_ has joined #yosys | 22:16 | |
| *** jfcaron_ is now known as jfcaron | 22:20 | |
| *** modwizcode has quit IRC | 23:39 | |
| *** Thorn has joined #yosys | 23:54 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!