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| z0ttel | How should I interpret this ltp line? Is that a real gate? "$abc$144686$new_n6219_ (via $abc$144686$auto$blifparse.cc:377:parse_blif$144697" | 09:39 |
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| az0re | z0ttel: Yes, it's a real gate, with name info mangled/replaced because it's the re-imported result of BLIF export from ABC | 16:12 |
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| kitten_nb_five | hello. just to make sure, is there something special to think about for a READ from an INOUT? for a write i need to enable the output that is tristated (16'hzzzz), but for a read i can simply assign the value to a reg [15:0] - or not? Lattice ECP5, Yosys and nextpnr | 19:11 |
| daveshah | Yeah a read should just work fine like that | 19:12 |
| kitten_nb_five | ok, thank you. | 19:12 |
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| matthuszagh | hello. is it possible to read a spice netlist with yosys? I'm only seeing a command to write a spice netlist | 19:20 |
| Lofty | matthuszagh: what would Yosys do with such a thing? It's not a SPICE program | 19:40 |
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| matthuszagh | Lofty: fair enough. just thought it might since it can write spice netlists. the use case is that a tool called netlistsvg can read yosys json netlists to draw schematics. i thought it might be possible to use this + yosys to draw ngspice netlists. but to your point, this really isn't yosys's use case | 20:18 |
| Lofty | It would be useful for it to output SPICE netlists after e.g. ASIC synthesis, but no real use in taking in SPICE netlists | 20:19 |
| Lofty | Same reason why Yosys doesn't support things like the Verilog pmos/nmos statements | 20:20 |
| matthuszagh | Lofty: ah ok that makes sense. thanks for clarifying | 20:20 |
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| thardin | making a lil' 200 MHz ADC pmod | 20:34 |
| thardin | I find digilent's catalog lacking | 20:35 |
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