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| awygle | yosys doesn't support "protected" verilog files does it? | 00:55 |
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| mwk | of course not | 02:08 |
| awygle | figured, thought i'd ask | 02:13 |
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| sameer_ | Test | 09:59 |
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| sameer_ | Test | 20:11 |
| daveshah | Test passed | 20:11 |
| sorear | huh, the logs are down | 20:12 |
| daveshah | I think tim runs a log too | 20:13 |
| thardin | just dropped off my ice40 based lock-in amplifier thingy at uni for feedback | 20:14 |
| daveshah | https://logs.timvideos.us/%23yosys/latest.log.html | 20:14 |
| tpb | Title: Wednesday, 2020-09-16 (at logs.timvideos.us) | 20:14 |
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| awygle | when you're not using multiclock, how do you specify the timestep yosys formal should use? i have some delays that are specified in nanoseconds that i want to prove hold | 23:16 |
| awygle | currently it seems to be using 100 MHz but idk if that's stable | 23:16 |
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