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Guest94 | need synthesizable RTL code | 08:38 |
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lofty[m] | for what? | 10:03 |
Guest94 | i need to test my synthesis script | 10:05 |
lofty[m] | https://github.com/YosysHQ/yosys-bench/tree/master/verilog/benchmarks_large/vexriscv | 10:06 |
Guest94 | already tested on one need to test bigger design that have lakhs of flops | 10:06 |
lofty[m] | uh, Yosys performs very badly with such | 10:07 |
Guest94 | thanks for link | 10:07 |
Guest94 | badly means? | 10:08 |
lofty[m] | slow runtime | 10:08 |
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vancz | mfw 800 eur registration fee for presenting a paper https://www.date-conference.com/registration | 15:51 |
tpb | Title: Registration & Participation | DATE 2025 (at www.date-conference.com) | 15:51 |
vancz | guess ill just stay in my shithole country | 15:52 |
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