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| trabucayre | I encounter a problem to simulate ECP5 code with specific hardware IP. see https://pastebin.com/b3QMWK37 The problem is not iverilog or my code but seems to be due to include problem. The missing file is present at the same level as cells_sim.v but not seen. | 15:09 |
|---|---|---|
| tpb | Title: iverilog -s testbench -o ecp5evndemo_tb.vvp ecp5evndemo_tb.v ecp5evndemo.v `yosy - Pastebin.com (at pastebin.com) | 15:09 |
| daveshah | There is a blackbox for USRMCLK in cells_bb.v | 15:09 |
| trabucayre | I suppose i'm wrong somewhere but where. | 15:09 |
| trabucayre | Yes and this one is in cells_bb.v | 15:10 |
| trabucayre | ok I need to add this file one. | 15:10 |
| trabucayre | due to the "Include file cells_ff.vh not found" I'm bit lost | 15:11 |
| daveshah | You need /usr/local/share/yosys/ecp5/ to be in the iverilog include path | 15:11 |
| trabucayre | It's work better! thanks | 15:16 |
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| aaaa | can yosys take switch-level verilog and reduce it to gate-level (even if inefficient) | 23:08 |
| aaaa | (switch level being pmos / nmos ) | 23:09 |
| DaKnig | how does switch level verilog look? | 23:10 |
| DaKnig | isnt it a bunch of primitives? | 23:10 |
| aaaa | pmos pmosA(out_net, 1, a); | 23:10 |
| aaaa | pmos pmosB(out_net, 1, b); | 23:10 |
| aaaa | pulldown pup(out_net); | 23:10 |
| aaaa | like this | 23:10 |
| aaaa | its primitives, but they're verilog builtins | 23:10 |
| DaKnig | then yosys would need to know how those "modules" behave | 23:11 |
| aaaa | yosys seems to be accepting them | 23:11 |
| aaaa | but opt/techmap/abc don't seem to acknowledge them | 23:11 |
| aaaa | wait nvm | 23:12 |
| whitequark | aaaa: no, as per https://github.com/YosysHQ/yosys/#unsupported-verilog-2005-features these are not supported and never will be | 23:13 |
| tpb | Title: GitHub - YosysHQ/yosys: Yosys Open SYnthesis Suite (at github.com) | 23:13 |
| DaKnig | what model are you even using to simulate pmos transistors? there are so many; I doubt a digital simulator/toolchain can understand this correctly in all cases | 23:13 |
| awygle | they're not real transistors. the verilog standard defines the model | 23:30 |
| awygle | at least that's my understanding | 23:30 |
| DaKnig | ah. I see. | 23:31 |
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