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Vuokko | Hi! | 16:18 |
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Vuokko | I have relaatively small problem. I need to do some about 60 volts switching matrix and it will be cominatorial logic. Can yosys synthesize this to discrete transistors? | 16:23 |
mwk | not really, but it can synthesize it to standard CMOS cells | 16:31 |
mwk | which can then trivially be broken down to transistors | 16:31 |
Lofty | Not even that | 16:32 |
Lofty | Yosys can either use Liberty cells | 16:33 |
Lofty | So if you write your own liberty cells, you can get a netlist | 16:34 |
Lofty | For example, I wrote a Liberty cell library for the 7400 logic family | 16:35 |
Vuokko | OK. I think I have seen that blog post | 16:36 |
Lofty | That hackaday article was on me and pepijndevos, yeah | 16:36 |
sorear | I'm a little unsure what you're trying to do, yosys will automate the process of telling you what logic gates to use to implement something described in verilog, but that's mostly useful if you have hundreds of them | 16:43 |
Vuokko | The system goes like this: I have an FPGA and there is my quick real time system. It is also the last place where I have pins left and those aren't just enough either. So I could make the last logic part with the power supply after all I'm controlling it | 16:48 |
Lofty | Partitioning logic is a tricky problem | 16:50 |
Vuokko | thanks for solving my problem. I totally forgot shift registers and latches in 7400 logics.I can solve with that my current problem. | 17:15 |
Lofty | Well, Yosys can't really map either | 17:17 |
Lofty | Latches are difficult because they're combinational | 17:17 |
Vuokko | but I also took a look at the the 7400-liberty project... I could try to write a tedax exporter for using pcb-rnd. do you have any json file available? I believe kicad exporter uses that | 17:17 |
Lofty | Vuokko: Yosys' write_json does exactly that | 17:17 |
Vuokko | I'm just lazy as I don't have yousys installed on this computer :) so that's why I asked for a file | 17:19 |
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