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| cr1901_modern | https://gist.github.com/cr1901/e870ac71283c792a20f6d4a0ee23cb37 Okay I'm reasonably happy with this script. Spent waaay too much time optimizing it, but it's worth it in the sense that I track upstream enough that I'll eventually make up the time | 00:37 |
|---|---|---|
| tpb | Title: FOSS FPGA Toolchain Build Script · GitHub (at gist.github.com) | 00:37 |
| cr1901_modern | whitequark: Btw, this didn't work for me (as part of a test) until I set ICE40_CHIPDB to "${CMAKE_CURRENT_BINARY_DIR}/chipdb" https://github.com/YosysHQ/nextpnr/blob/master/ice40/CMakeLists.txt#L88 | 00:45 |
| tpb | Title: nextpnr/CMakeLists.txt at master · YosysHQ/nextpnr · GitHub (at github.com) | 00:45 |
| cr1901_modern | err ECP5_CHIPDB*, but it's analogous | 00:45 |
| whitequark | cr1901_modern: oh, that's prob a typo | 00:46 |
| whitequark | think you can send a PR? | 00:46 |
| cr1901_modern | Yes, give me a minute and I will | 00:47 |
| cr1901_modern | whitequark: https://github.com/YosysHQ/nextpnr/pull/491 | 01:15 |
| tpb | Title: Fix MESSAGE indicating where externally-built .bbas live. by cr1901 · Pull Request #491 · YosysHQ/nextpnr · GitHub (at github.com) | 01:15 |
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| thardin | dkozel: haven't looked at gr internals yet, but sounds promising | 10:24 |
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| thardin | does yosys not implement $fdisplay? I tried enabling systemverilog. no dice | 13:43 |
| thardin | I'd like my assertion messages to go to stderr, and/or to show up even with yosys -q | 13:43 |
| daveshah | Have you tried $error, outside of a block ? | 13:46 |
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| thardin | I can do $error outside initial, yes | 13:51 |
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| thardin | oh, it's the $finish tripping it up | 13:53 |
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| thardin | `define assert(signal, value) if (signal !== value) $error({"ASSERTION FAILED: ", `"signal`", " != ", `"value`"}); | 13:55 |
| thardin | works | 13:55 |
| thardin | `define assert(cond) if (!(cond)) $error({"ASSERTION FAILED: ", `"cond`"}); | 13:57 |
| thardin | even simpler | 13:57 |
| DaKnig | can yosys spit out vhdl? | 14:15 |
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| lambda | DaKnig: afaik no, not even with verific - there's a WIP at https://github.com/ghdl/ghdl-yosys-plugin/pull/122, but that's definitely not ready yet | 14:44 |
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| thardin | http://blog.notdot.net/2012/10/Build-your-own-FPGA fun | 20:24 |
| tpb | Title: Build your own FPGA - Nick's Blog (at blog.notdot.net) | 20:24 |
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| Lofty | Why stop at that? | 20:28 |
| Lofty | I wrote a Yosys script to synthesise Verilog into 74xx logic | 20:29 |
| tnt | still waiting for that 7400 riscv :p | 20:34 |
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