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| pepijndevos | How well does Yosys support division? | 09:07 |
|---|---|---|
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| daveshah | My experience is that anything other than a power of two ends up with a massive circuit | 09:31 |
| daveshah | Sometimes abc9 does clean things up a bit | 09:31 |
| pepijndevos | daveshah, yea I guess that is to be expected. But from what I read some synthesis tools outright don't support anything other than powers of two, or maybe constants only or stuff like that. | 09:45 |
| daveshah | Yosys will bravely try and synthesis any divide | 09:46 |
| pepijndevos | Cool | 09:46 |
| pepijndevos | Maybe in the end I will implement a sequential division if it turns out to be too unreasonable. | 09:46 |
| Lofty | It'll also attempt combinational modulus too, I think | 09:47 |
| daveshah | Yep | 09:47 |
| daveshah | I suspect there are much better combinational algorithms than the one Yosys uses | 09:48 |
| daveshah | But I haven't looked into it in detail | 09:48 |
| daveshah | Even if you do want single cycle divide, often it needs to be pipelined so you wouldn't infer it anyway | 09:48 |
| pepijndevos | Just because it's so unwieldy it drives fmax down the drain? | 09:50 |
| Lofty | Pretty much | 09:51 |
| pepijndevos | Hm, pipelining only gets you more throughput, not more latency, right... | 09:52 |
| pepijndevos | (compared to normal clocked) | 09:53 |
| Lofty | pepijndevos: for the specific path, latency generally goes up. But because your division is no longer part of the critical path, effective latency everywhere else goes down :P | 09:55 |
| pepijndevos | I mean latency in "number of clock cycles to complete calculation" not in the timing sense, but yea | 09:56 |
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| * promach3 uploaded an image: image.png (280KiB) < https://matrix.org/_matrix/media/r0/download/matrix.org/CaEWbKsdHnqMAgupUfLMoAqw/image.png > | 13:12 | |
| promach3 | For https://github.com/promach/noc/blob/development/spidergon_node.v#L475 , why formal verification failed for this BMC basecase assert() ? | 13:12 |
| tpb | Title: noc/spidergon_node.v at development · promach/noc · GitHub (at github.com) | 13:12 |
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| Forty-Bot | is there a way to indicate "don't care" in combinatorial logic? | 18:01 |
| Forty-Bot | e.g. this stackoverflow question https://stackoverflow.com/questions/29451175/how-can-i-assign-a-dont-care-value-to-an-output-in-a-combinational-module-in | 18:01 |
| tpb | Title: How can I assign a "dont care" value to an output in a combinational module in Verilog - Stack Overflow (at stackoverflow.com) | 18:01 |
| Forty-Bot | one answer is for quartus, however when I try the same thing in yosys the "don't cares" get interpreted as zeros | 18:02 |
| mwk | just use x bits, they are supported | 18:12 |
| mwk | (yosys might miss some optimization opportunities though) | 18:13 |
| Forty-Bot | ok, so for that example, bit 0 synthesizes as an and gate | 18:19 |
| Forty-Bot | but since it is don't-care, it should synthesize as a constant 1 | 18:20 |
| Forty-Bot | which to me means that the Xs are interpreted as 0s and not "don't care"s | 18:20 |
| mwk | look | 18:20 |
| mwk | "don't care" means that synthesis can pick any bit it wants | 18:20 |
| mwk | it picked 0 in this case, this is not an error | 18:20 |
| Forty-Bot | right, and I want it to pick a bit which minimizes the amount of area | 18:21 |
| Forty-Bot | instead of picking any bit it wants | 18:21 |
| mwk | yeah, it seems yosys has no optimization pass that'd be able to figure this out | 18:25 |
| Forty-Bot | :l | 18:25 |
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| mwk | it is an interesting case though | 18:29 |
| mwk | I think whitequark had a draft pass (opt_match?) that would solve it nicely | 18:29 |
| whitequark | yes | 18:30 |
| whitequark | and i actually know how to properly put it into yosys now | 18:30 |
| whitequark | like, in a way that would get it merged and nicely intregrated with the existing passes, rather than a total rewrite of proc i initially planned (which is unnecessary anyway, at least for the reasons i wanted it) | 18:31 |
| mwk | do you want it as an extra opt pass, or an extra proc pass? | 18:31 |
| whitequark | extra proc pass | 18:32 |
| mwk | huh. | 18:32 |
| whitequark | either that or mmm | 18:32 |
| whitequark | i think it would actually be a new mode for proc_mux | 18:32 |
| mwk | right, proc_mux replacement | 18:32 |
| whitequark | the idea is to ditch everything i wrote for proc_match except for the, well, match-related parts | 18:33 |
| whitequark | all the stuff i did for mux insertion was really clever... clever enough i never figured out how to make it work | 18:33 |
| whitequark | and tbh | 18:33 |
| whitequark | it's possible that with better column order selection the rest of yosys will cope just fine | 18:33 |
| whitequark | possibly not but i don't want to prematurely rewrite it | 18:33 |
| mwk | (I might have a refactor of proc incoming for unrelated reasons though — better async reset support) | 18:33 |
| mwk | (the main idea being that proc_dff / proc_dlatch should run *before* proc_mux and be merged with proc_arst, to remove some current weirdness with async resets in DFFs and support resets in dlatches) | 18:35 |
| whitequark | uh, that might actually break nmigen | 18:36 |
| whitequark | i'm not saying you shouldn't | 18:36 |
| mwk | huh, why? | 18:36 |
| whitequark | i'm saying you might | 18:36 |
| whitequark | wait | 18:36 |
| whitequark | nevermind, i misremembered | 18:36 |
| whitequark | (because nmigen uses proc_arst;proc_dff, but i misremembered that it just uses proc_arst alone) | 18:36 |
| mwk | oh, you're actually using proc_* subpasses on their own, without the proc wrapper? | 18:37 |
| whitequark | yes | 18:37 |
| mwk | ... okay, that has a good chance of breaking | 18:37 |
| whitequark | yes | 18:38 |
| whitequark | the reason i do that is because i want write_verilog to get a netlist it can actually process | 18:38 |
| whitequark | but i don't want processes to be bitblasted away | 18:38 |
| whitequark | tbh | 18:38 |
| whitequark | if there was a `proc -nomux` it's likely i could just use that | 18:39 |
| mwk | hmmmm, that sounds good | 18:39 |
| Forty-Bot | so is there any other approach to doing this other than hand-optimization? | 18:42 |
| Forty-Bot | especially with much bigger cases | 18:42 |
| mwk | not really, this is the obvious pattern | 18:43 |
| mwk | we just need more optimization power | 18:43 |
| Forty-Bot | oof | 18:43 |
| whitequark | mwk: https://github.com/nmigen/nmigen/issues/479 | 18:43 |
| tpb | Title: Add `proc -nomux` to Yosys and migrate to it · Issue #479 · nmigen/nmigen · GitHub (at github.com) | 18:44 |
| whitequark | Forty-Bot: people sometimes automate it | 18:44 |
| Forty-Bot | yeah, I was reading https://static.docs.arm.com/arp0009/a/Verilog_X_Bugs.pdf and in section 7.2 they say to just shove it through an optimizer | 18:44 |
| Forty-Bot | though apprently espresso has not been updated since 2008 | 18:45 |
| mwk | ... heh | 18:52 |
| mwk | of course skipping proc_mux breaks latches | 18:53 |
| whitequark | that might be why i don't run proc_dlatch | 18:54 |
| mwk | yeah, I suppose you don't care about them anyway | 18:54 |
| Forty-Bot | ok, so is it possible to get yosys to enumerate the inputs/outputs of a design in a truth table, or would I need to write that myself? | 18:59 |
| mwk | there's the eval pass, but I'm not sure that's what you have in mind | 19:01 |
| Forty-Bot | e.g. anything close to what this thing inputs http://users.ece.utexas.edu/~patt/06s.382N/tutorial/espresso_manual.html | 19:01 |
| tpb | Title: EE 382N - Espresso Manual (at users.ece.utexas.edu) | 19:01 |
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| Lofty | Way too late, but Forty-Bot, you should really consider using ABC. | 21:11 |
| Forty-Bot | how would I do that? | 21:11 |
| Lofty | Yosys bundles it as yosys-abc | 21:11 |
| Forty-Bot | I tried playing around with the options, but "undef" values in the blif seemed to get removed even with an empty script | 21:12 |
| Lofty | Well, I can't remember what the Yosys ABC pass does, but I think it dumps to AIGER | 21:13 |
| Lofty | Which doesn't support DC | 21:13 |
| Forty-Bot | by default it reads/writes blif in yosys | 21:13 |
| Lofty | ABC9 goes through XAIGER, I know that much | 21:13 |
| Forty-Bot | anyway, what do you suggest I look into for optimizing dontcares? | 21:14 |
| Lofty | ...ABC. | 21:14 |
| Forty-Bot | yes, and ABC has something like 100 commands | 21:15 |
| Lofty | Don't use the Yosys internal pass | 21:15 |
| Lofty | Grab abc.rc from https://github.com/berkeley-abc/abc/blob/master/abc.rc | 21:15 |
| tpb | Title: abc/abc.rc at master · berkeley-abc/abc · GitHub (at github.com) | 21:15 |
| Lofty | Then run resyn2 a bunch of times, as I understand it | 21:16 |
| Forty-Bot | haha | 21:16 |
| Lofty | Most (&if is a sad exception) commands have -h for help | 21:17 |
| Forty-Bot | thanks for the tip | 21:18 |
| Lofty | I think ABC might read DCs separately | 21:18 |
| Lofty | BLIF is a mostly theoretically interchangeable format | 21:20 |
| Lofty | And I think this proves it quite well :P | 21:20 |
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