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| nmz787 | nor this: assign {RED[3], RED[2], RED[1], RED[0]} = {P1A4, P1A3, P1A2, P1A1}; | 00:01 |
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| nmz787 | is this assignment style really only SystemVerilog?? | 00:01 |
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| mwk | wire [3:0] RED = {P1A4, P1A3, P1A2, P1A1}; | 00:38 |
| mwk | or if RED is already declared, assign RED = {P1A4, P1A3, P1A2, P1A1}; | 00:39 |
| nmz787 | mwk: oh, weird, I guess I had the bit-range on the wrong side of the variable name | 00:42 |
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