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| tnt | Is there a way to guide yosys/abc to use a given cell to synthesize adders ? the cell library has a full adder cell but it's not used for adders when just feeding the liberty file. | 21:31 |
|---|---|---|
| daveshah | nope, abc can't map multi output cells | 21:31 |
| daveshah | you can use Yosys' extract_fa and techmap, but then you lose all of the abc optimisations, buffer sizing, timing, et | 21:32 |
| daveshah | *etc | 21:32 |
| daveshah | the cost of doing that is probably higher than the benefit of using an adder cell, Yosys should use a fairly good algorithm for adders anyway | 21:32 |
| Lofty | daveshah: or techmap $alu (though with full adder cells it's a bit questionable) | 21:46 |
| daveshah | Yeah, and it still has the same downsides | 21:49 |
| daveshah | adder mapping is certainly a lot less important in asic than in fpga | 21:49 |
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