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| az0re | So, before I go check for myself, does anyone know off the top of their head how would a Verilog always block with complete case statement get translated to RTLIL? Would it make a mux tree? | 08:24 |
|---|---|---|
| az0re | assuming `proc; opt; techmap` were called after `read_verilog` | 08:26 |
| az0re | Or would it instantiate, say, pmuxes with $eq cells on the select lines? | 08:32 |
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| Lofty | az0re: a complete case is probably turned into the latter | 09:20 |
| Lofty | Incomplete cases would probably be mux trees due to the Verilog standard requiring ordering | 09:21 |
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| az0re | Lofty: Thanks | 17:33 |
| Lofty | np | 17:33 |
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| az0re | Indeed, it looks like a pmux with $eq cells on the select lines, except for case zero which has $logic_not on the select line | 20:00 |
| az0re | I am a little confused, actually. What exactly is the behavior of pmux? | 20:01 |
| az0re | For each bit i, z[i] = s[i]? b[i] : a[i] ? | 20:03 |
| az0re | No | 20:03 |
| az0re | nvm I found it in the manual | 20:07 |
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| mwk | pepijndevos: ping | 22:25 |
| Lofty | I don't think pepijndevos will be around at this hour, mwk | 22:27 |
| mwk | well I need a gowin question answered... | 22:28 |
| Lofty | About DFFs? | 22:28 |
| mwk | yes | 22:28 |
| mwk | the one I asked a few days ago | 22:28 |
| Lofty | ... Lemme ping him on Twitter | 22:29 |
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| ananan | how do i get yosys to generate the hierarchy if i used -defer in read_verilog? | 23:52 |
| ananan | i tried doing `hierarchy` and `hierarchy -check -top top` but neither worked | 23:52 |
| ananan | (after that is `synth_ecp5 -json json.out -top top` and it generates a json with no modules) | 23:53 |
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