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| ananan | Is there a dedicated channel for symbiyosys / formal (specifically riscv-formal stuff) or is this the best place? | 01:49 |
|---|---|---|
| ananan | and/or has anyone here used riscv-formal? | 01:49 |
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| awygle | this is the best place, probably | 02:09 |
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| thardin | morning | 08:14 |
| thardin | how do you all do testing of your designs? I'm considering something like every module foo.v having a test_foo.v test bench, and write_verilog synth_foo.v from yosys | 08:20 |
| thardin | and do both iverilog test_foo.v foo.v and iverilog test_foo.v synth_foo.v | 08:20 |
| thardin | and maybe a reference output for each module | 08:21 |
| strubi | Testing, ha. I ended up running things through a jupyter notebook and some py.test framework | 08:21 |
| strubi | (using pyosys API) | 08:22 |
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| thardin | haven't had too much problem with the actual verilog so far, it's mostly the numerics/dsp stuff that's tricky | 09:16 |
| thardin | but being reasonably sure none of the I/O stuff or lower-level modules work as expected is less mental load :) | 09:16 |
| strubi | implicit sign extension and that sort? they keep being painful... | 09:22 |
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| strubi | Not sure, no vegan i am | 09:25 |
| strubi | whoops | 09:25 |
| thardin | nah more like control loops and such | 09:26 |
| thardin | integration blowing up | 09:26 |
| thardin | those sorts of things | 09:26 |
| thardin | sign extension problems can be caught statically. purely numeric issues are hard to prove/disprove by machine | 09:27 |
| strubi | but that doesn't sound too HDL specific, you'll just have to pinpoint eventuall discrepancies between numerical model and HW implementation (and hope your vendor models are right) | 09:31 |
| strubi | I am putting coffee into my throat now. Not trusting fully sized avocados yet. | 09:45 |
| strubi | Argh... I'm dumb. These windows.. | 09:46 |
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| thardin | "vegans after dark" :] | 12:09 |
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| thardin | are there any dev boards with the HX8K? | 14:42 |
| daveshah | There's the mystorm BlackIce which is hx4k (8k die) | 14:43 |
| tnt | icoboard maybe ? | 14:43 |
| thardin | http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard | 14:43 |
| tpb | Title: iCE40-HX8K Breakout Board - Lattice Semiconductor (at www.latticesemi.com) | 14:43 |
| thardin | I can probably squeeze my design down to 1k in due time, but I don't want to have to while I'm still experimenting | 14:44 |
| thardin | https://www.electrokit.com/produkt/olimex-ice40hx8k-fpga-utvecklingskort/ | 14:45 |
| tpb | Title: Köp Olimex iCE40HX8K FPGA utvecklingskort till rätt pris @ Electrokit (at www.electrokit.com) | 14:45 |
| thardin | looks like it uses the AVRISP connector for programming? | 14:46 |
| thardin | icoboard looks interesting | 14:49 |
| thardin | can it be programmed without a pi? | 14:53 |
| daveshah | yes there is a USB baseboard for it | 14:54 |
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| thardin | link? looking at https://www.digikey.se/sv/product-highlight/t/trenz/carrier-boards right now | 14:59 |
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| thardin | taking a look at the 32c3 talk about it | 15:09 |
| thardin | I do have an extra pi laying around, but it would be nice to have fewer things inbetween | 15:15 |
| strubi | why not just use one of the omnipresent FT2232 boards? | 15:21 |
| thardin | if that works then sure. I have one of those even | 15:21 |
| thardin | haven't dived into the icoboard documentation yet :) | 15:23 |
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| strubi | and someone has changed what? | 16:02 |
| strubi | (pls ignore again) | 16:03 |
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| thardin | what's the tool to program the arty board again? | 18:58 |
| daveshah | xc3sprog? | 18:59 |
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| thardin | I'll give it a look, thanks | 19:00 |
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| thardin | we have blinkenlights! :) | 19:03 |
| thardin | xc3sprog -c nexys4 blinky.bit was the invocation | 19:03 |
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| lambda | thardin: https://github.com/trabucayre/openFPGALoader is an alternative that's less dead | 19:17 |
| tpb | Title: GitHub - trabucayre/openFPGALoader: Universal utility for programming FPGA (at github.com) | 19:17 |
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| bwidawsk | m/][i | 19:23 |
| thardin | lambda: noted | 19:25 |
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| thardin | should I be concerned that nextpnr-xilinx doesn't complain about ports not being assigned properly? it compiles my code for the iceblink board just fine, even with me not having set up all the PMOD pins yet | 19:34 |
| daveshah | It is missing loads of error checking | 19:35 |
| thardin | I gets output like "Info: IO port 'PMOD1' driven by IBUF '$auto$iopadmap.cc:409:execute$36570'" | 19:35 |
| thardin | ah ok | 19:35 |
| daveshah | There is a very good reason it isn't upstream (and at the current rate may never end up upstream) | 19:35 |
| thardin | found digilent's xdc files, so I should hopefully get something going | 19:39 |
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| thardin | I get SCLK on my DAC at the speed I expect. wrong pin though, but that can be fixed tomorrow | 20:24 |
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| awygle | do conditional cover statements make sense? is there a difference between `cover(a&b)` and `if a: cover(b)`? does the latter even work? | 20:42 |
| mwk | I don't suppose we have someone who knows the clk2fflogic pass here? | 20:49 |
| mwk | I'd really like to know why it transforms the $adff cell to effectively use `ARST || $past(ARST)` instead of just `ARST` as the reset | 20:49 |
| mwk | and, for that matter, why it doesn't do such a thing on $dffsr | 20:50 |
| daveshah | I think this was to fix some slightly confusing behaviour, I remember it being discussed with claire at one point | 20:51 |
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| daveshah | the trigger was this rather vague reddit post https://www.reddit.com/r/yosys/comments/c8ioug/asynchronous_reset_mechanism_of_d_flipflop_in/ | 21:01 |
| tpb | Title: asynchronous reset mechanism of D flip-flop in yosys : yosys (at www.reddit.com) | 21:01 |
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