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| daveshah | ross_s: https://github.com/YosysHQ/nextpnr/pull/454 should fix the global routing issue on the nextpnr side now | 14:48 |
|---|---|---|
| tpb | Title: ecp5: Fix placement of DCCs to guarantee routeability by daveshah1 · Pull Request #454 · YosysHQ/nextpnr · GitHub (at github.com) | 14:48 |
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| llee454 | Good morning. Is anyone free to answer a question I have about using Yosys to generate BLIF files for arachne-pnr? I'm getting the following error from arachne: "kami32.blif:11: fatal error: invalid .names entry: both gates must be 1 here" | 15:21 |
| daveshah | How are you generating the BLIF? | 15:25 |
| llee454 | I used the interactive shell to enter the following sequence of commands: read_verilog "kami32.v"; hierarchy -check -top _design; proc; memory; techmap; abc; write_blif "kami.blif" | 15:26 |
| llee454 | Also thanks for offering to help. | 15:27 |
| daveshah | you need to use synth_ice40 | 15:27 |
| daveshah | arachne-pnr doesn't support generic primitives, it places and routes for iCE40 so needs the iCE40 specific primitives | 15:28 |
| llee454 | I see. | 15:28 |
| daveshah | specifically "synth_ice40 -blif out.blif" | 15:28 |
| daveshah | which gives some extra arguments to write_blif to make it arachne-pnr compatibke | 15:28 |
| daveshah | *compatible | 15:28 |
| llee454 | Thanks daveshah I'm going to try this now. | 15:29 |
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| llee454 | daveshah, I tried to run "synth_ice40," but ran out of RAM during the peepopt pass. I then copied the commands listed here (http://www.clifford.at/yosys/cmd_synth_ice40.html) into a script file, commented out the peepopt pass, and ran the script. This generated a blif file. But, arachne-pnr returned the following error message for it: | 17:29 |
| llee454 | "kami32.blif:88146: fatal error: unknown model `$__ICE40_CARRY_WRAPPER'" Any ideas? | 17:29 |
| tpb | Title: Yosys Open SYnthesis Suite :: Command Reference :: synth_ice40 (at www.clifford.at) | 17:29 |
| daveshah | There shouldn't be $__ICE40_CARRY_WRAPPERs in the output but this is possibly an issue with whiteboxes | 17:30 |
| daveshah | The running out of RAM issue is probably more serious, assuming your system has a reasonable amount of free RAM | 17:30 |
| mwk | hmmm, peepopt... | 17:30 |
| llee454 | The exact commands I used were: https://hastebin.com/payemikuqa.cs | 17:30 |
| tpb | Title: hastebin (at hastebin.com) | 17:30 |
| daveshah | the `only if relut` comment might be out of date, try re-enabling ice40_unlut | 17:31 |
| llee454 | yosys was consuming 14GB when it died running peepopt. Is this normal for a large design? | 17:31 |
| llee454 | ok | 17:31 |
| daveshah | not for any design that fits on an iCE40 or ECP5 | 17:32 |
| daveshah | (for perspective, a Rocket design that maxes out a Versa peaks at around 1GB) | 17:32 |
| whitequark | do you maybe have a RAM that got legalized into FFs? | 17:33 |
| ZipCPU | Or some multiplies that didn't get placed into DSPs? | 17:33 |
| llee454 | rerunning with "ice40_unlut; opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3" | 17:33 |
| tnt | Yeah, non-inferred bram would be my guess. | 17:34 |
| ZipCPU | It might also help to run on the yosys on the various components of your design. Chances are there's one component that's using way too many resources | 17:34 |
| ZipCPU | Just doing that component would likely fit in memory | 17:34 |
| llee454 | I see. | 17:34 |
| daveshah | If other commands run fine, then it isn't a design problem but a peepopt problem | 17:34 |
| llee454 | I will try to run yosys on the various components and see how much RAM it consumes. | 17:34 |
| llee454 | daveshah the other commands appear to run fine. | 17:35 |
| mwk | llee454: I'd be interested in having a look at that design | 17:40 |
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| llee454 | The documentation for the synth_ice40 pass is out of date. The documentation says that the pass calls ice40_unlut, but ice40_unlut no longer exists. There is a pass named "ice40_wrapcarry" however. The shell documentation says that this pass accepts a flag named "-unwrap," which looks like it might resolve the error returned by Arachne. I'm | 17:46 |
| llee454 | recommenting out the ice40_unlut pass and adding a call to wrapcarry. | 17:46 |
| llee454 | @mwk sure. One moment. | 17:46 |
| mwk | llee454: FWIW for a current list of commands executed by the pass, you can always run yosys -p 'help synth_ice40' | 17:47 |
| mwk | this applies to most yosys script passes | 17:47 |
| llee454 | @mwk thanks. I see that this includes a call to unwrap. I will use that and comment out peepopt. | 17:48 |
| mwk | ... would be nice to know which of the three peepopt sub-passes causes the problem | 17:48 |
| mwk | but uh, seems we don't even have a way at the moment to execute a subset of thoser | 17:49 |
| ross_s | daveshah: thanks for following up, I just re-broke my design and verified that it failed to route on my current version / succeeds to route on nextpnr master, so patch seems good! | 17:50 |
| daveshah | Thanks for testing! | 17:51 |
| llee454 | @mwk https://github.com/llee454/RiscvSpecFormal/blob/temp/verilog-models/kami32.v | 17:56 |
| tpb | Title: RiscvSpecFormal/kami32.v at temp · llee454/RiscvSpecFormal · GitHub (at github.com) | 17:56 |
| llee454 | @mwk note: that the verilog is generated by compiling a model written in Kami. The Kami model is divided into a set of files in the ProcKami directory. Somewhat confusingly both verilog and Kami use the same file extension - ".v" | 17:57 |
| mwk | hmm | 17:59 |
| mwk | how do I trigger the issue? "yosys -p synth_ice40 kami32.v"? | 17:59 |
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| mwk | peepopt seems to work just fine for me | 18:00 |
| mwk | otoh, it gets stuck soon afterwards in the `share` pass and ate 16GB of memory so far | 18:01 |
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| mwk | yeah, OOM-killed in share at 27GB memory usage | 18:03 |
| mwk | peepopt worked just fine though, and semi-instantly as well | 18:03 |
| llee454 | @mwk Yes. I just noticed that I misattributed the point of failure. | 18:04 |
| llee454 | @mwk apparently it was the share pass that consumed the excess memory. | 18:04 |
| tnt | The RAM have resets. | 18:05 |
| tnt | Although removing it doesn't really help either. | 18:06 |
| whitequark | what if you mark the RAM as (*ram_block*)? | 18:07 |
| llee454 | @tnt I thought that the hierarchy pass strips out the two memory devices. | 18:07 |
| tnt | llee454: mmm maybe, I didn't try the full synth, I figured if it was in the verilog, it'd be used ... | 18:08 |
| llee454 | I see. I'll try removing them explicitly if my current run fails. | 18:09 |
| tnt | So the top level is _design and not _system ? | 18:09 |
| tnt | did you select that as the top level ? | 18:09 |
| mwk | ... what exactly emitted this thing? | 18:10 |
| llee454 | @tnt yes. I only care about _design right now. My goal was just to confirm that the build system would work and that the processor core would fit. | 18:10 |
| mwk | because uh I'm not convinced it's actually valid verilog | 18:10 |
| mwk | yosys emits craploads of lines like "kami32.v:58620: Warning: Identifier `\tmp$818.valid' is implicitly declared." | 18:11 |
| llee454 | @mwk './doGenerate.sh --verilog-sim --xlen 32' This command compiles the Kami code and generates System Verilog. Then I used sv2v to convert the System Verilog into Verilog. The kami32.v file is the result of this build process. | 18:11 |
| mwk | and, indeed, I have no idea what that is supposed to be — a bitfield of tmp$818 perhaps? but tmp$818 is just a plain 34-bit wire... | 18:12 |
| mwk | ... well, then it seems that sv2v is emitting bullshit | 18:12 |
| mwk | looks like a not-quite-converted SV structure to me | 18:12 |
| mwk | I mean, the OOM in `share` is still worrying and I'll try to investigate it, but it seems you have bigger problems | 18:13 |
| llee454 | @mwk hmm. Do you know of a better utility for converting System Verilog to Verilog? Yosys's System Verilog frontend chocked on the arrays in the original file. | 18:13 |
| mwk | not really | 18:13 |
| tnt | Although really to answer you question ... pretty sure it won't fit in any ice40 :p | 18:14 |
| daveshah | yeah the 7.9MB kind of gives that away already | 18:14 |
| tnt | :) | 18:14 |
| llee454 | @daveshah what size range would the Verilog file have to fit in to be viable? | 18:15 |
| llee454 | Also are there plans to expand support for System Verilog arrays? | 18:15 |
| daveshah | there's no exact range, it's just a feeling | 18:15 |
| llee454 | I might be willing to help add that support. What would be involved? | 18:15 |
| tnt | Where does that verilog even comes from ? | 18:17 |
| llee454 | Well for what it's worth, I got arachne to report a new error: https://hastebin.com/ibovulopeg.rb | 18:18 |
| tpb | Title: hastebin (at hastebin.com) | 18:18 |
| daveshah | maps to 17k LUT4s at the end with share commented out so it's over 2x too big for an ice40 anyway | 18:18 |
| daveshah | that's because you have more pins than the device has | 18:18 |
| daveshah | but the number of logic cells/LUTs is a bigger problem | 18:18 |
| tnt | LCs 22737 / 7680 | 18:19 |
| tnt | lol | 18:19 |
| llee454 | I used: https://hastebin.com/usohaforen.cs, where I just commented out the share pass (as well as other passes controlled by flags). | 18:19 |
| tpb | Title: hastebin (at hastebin.com) | 18:19 |
| tnt | BRAMs 0 / 32 | 18:19 |
| tnt | That's worrying. | 18:20 |
| tnt | sv2v probably screwed up inferrence. | 18:20 |
| llee454 | I see. | 18:20 |
| llee454 | Well, the only reason I used sv2v was because Yosys couldn't handle the arrays in my system verilog file. Perhaps it would be wiser for me to add support for arrays. Can anyone tell me (at a high level of abstraction) what this would entail? | 18:22 |
| tnt | what kind of array ? | 18:22 |
| mwk | hmm | 18:23 |
| mwk | how old is your yosys, anyway? | 18:23 |
| tnt | also did yo uuse the -sv flag | 18:23 |
| llee454 | Yosys 0.9+2406 (git sha1 9a2cf5e3, clang 6.0.0-1ubuntu2 -fPIC -Os) | 18:23 |
| llee454 | I just tried the -sv flag. No luck: https://hastebin.com/ilevekigag.coffeescript | 18:25 |
| tpb | Title: hastebin (at hastebin.com) | 18:25 |
| tnt | can you show ystem.sv ? | 18:25 |
| llee454 | The error is on line 5: https://hastebin.com/yovevekoqe.md | 18:27 |
| tpb | Title: hastebin (at hastebin.com) | 18:27 |
| mwk | so... not an array, just a multi-dimensional wire | 18:28 |
| tnt | Ah yeah, arrays in ports, yeah that's not going to work. | 18:28 |
| llee454 | Is there anything I can do to add support? Is there a conversion I can apply to the Verilog file to work with Yosys? | 18:29 |
| tnt | yeah you can flatten it ... change it to a [31:0] | 18:29 |
| tnt | (obviously you need to change it everywhere it's used ...) | 18:30 |
| llee454 | Thanks | 18:30 |
| llee454 | I assume that I need to do the same for packed structs? | 18:31 |
| llee454 | Yosys doesn't appear to like line 7 either. | 18:32 |
| tnt | All of that is in the "System" which you don't care about so maybe focus on fixing "Design" ... | 18:35 |
| llee454 | Thanks to everyone who offered me assistance. I'm going to revise the Kami compiler/design to avoid outputing packed structs and multidimensional wires. Hopefully that will result in parsable System Verilog code (even if the design remains too large to fit in an ice40 board). | 18:38 |
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