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| az0re | whitequark, you around? | 03:29 |
|---|---|---|
| az0re | It looks like RUSAGE_CHILD is not the solution. I modified it to use RUSAGE_CHILD and still don't see proper measurement. The man page says, "Return resource usage statistics for all children [...] that have terminated and been waited for" | 03:32 |
| az0re | Hmm, wait, maybe I'm wrong, I still see RUSAGE_SELF in the strace output for some reason... | 03:35 |
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| az0re | Yeah indeed I fucked it up somehow, nevermind | 04:06 |
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| Lofty | lambda: I think you might as well start writing code and see where that leads | 09:25 |
| lambda | Lofty: I honestly have better uses for my time than writing code that may or may not be thrown out for arbitrary reasons | 09:26 |
| whitequark | lambda: i'll raise the question re: memories at the next yosys meeting | 09:26 |
| whitequark | which i think happens next week | 09:26 |
| lambda | whitequark: thanks <3 | 09:26 |
| whitequark | and i agree that design discussion should happen before writing code, for something like this at least | 09:26 |
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| thardin | starting to get the hang of verilog and making smaller and faster designs | 11:51 |
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| Lofty | thardin: it's a tricky thing | 12:07 |
| thardin | ye. especially when you need to do initialization of some chips | 12:07 |
| thardin | I've ordered myself some more pmods. the max11300 one I have is too much hassle for now | 12:08 |
| thardin | but very versetile if I could get it working the way I want | 12:08 |
| thardin | in the timing output after routing, <async> means combinatorics right? | 12:59 |
| whitequark | i think it means "no clock domain known to nextpnr" | 13:00 |
| thardin | hmm | 13:01 |
| thardin | Info: Clock 'PMOD1$SB_IO_OUT_$glb_clk' has no interior paths | 13:02 |
| thardin | "normally this warning is a result of a design being optimised away excessively" | 13:06 |
| thardin | alright so it's just yosys doing a good job :) | 13:07 |
| thardin | woo my pmods have been shipped | 13:08 |
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| tnt | So yosys has `ltp`. But is there a way to get a histogram of the paths ? Like that many of length N, that many of length N-1, etc ... ? | 17:43 |
| whitequark | probably not, would be cool to have | 17:45 |
| az0re | +1 | 17:45 |
| whitequark | in fact i would even add that to the `check` label of synth scripts | 17:46 |
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| ross_s | Has anyone ecountered / got tips for debugging nextpnr when it stalls? I have a design that gets to 'Setting up routing queue', then after 5000-9000 IterCnt busy loops indefinitely. | 19:00 |
| ross_s | the position where it stalls seems to be consistent for a given input json | 19:01 |
| ross_s | randomly sampling the program by interrupting under gdb while in this state always seems to return nextpnr_ecp5::Arch::route / nextpnr_ecp5::router1 / (anonymous namespace)::Router1::route_arc, pip values do seem to be different each time so if it is stuck in a cycle it's not an immediately obvious one (to me at least) | 19:03 |
| Lofty | daveshah: ^ | 19:05 |
| Lofty | The main tip I have for debugging nextpnr is to ping Dave about it :P | 19:05 |
| tnt | ross_s: how full is the device ? | 19:05 |
| daveshah | Run with --debug --verbose | 19:06 |
| ross_s | in terms of trellis slice, ~35% | 19:06 |
| daveshah | that will print what the router is doing | 19:06 |
| ross_s | sorry for the delay, computer chugging a bit. The output has slowed for arcs such as the following: Routing arc 0 on net wb_intercon0.wb_arbiter_spi0.wbs_ack_i_LUT4_A_1_Z_LUT4_A_Z_LUT4_C_Z_LUT4_D_Z_TRELLIS_FF_DI_Q[1] (1 arcs total): | 19:11 |
| ross_s | I can kill and paste the full output somewhere if that's useful, or just the segment around that line | 19:11 |
| ross_s | http://public.rhye.org/route.log | 19:13 |
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| deadman | hi all, i'm trying to use two PLLs on the TinyFPGA board but can't seem to have both of them placed: "couldn't be placed anywhere, no suitable BEL found." | 19:38 |
| deadman | I know there's some restrictions based on the IOs used and stuff, but I can't seem to figure out a solution given that the onboard oscillator is stuck to pin B2 | 19:39 |
| ross_s | Which TinyFPGA board? If it's the BX, I think that the LP8K only has 1PLL in the 81ucBGA package | 19:39 |
| deadman | the first clock, I have to derive from the onboard oscillator. The second is derived from the output of the first, is that possible? | 19:40 |
| deadman | Yes, the BX, oh! | 19:40 |
| deadman | *facepalm | 19:40 |
| ross_s | It's a bit sneaky, looking at the ice 40 datasheet it says 2, but if you follow the annotation there's a note at the bottom about that package | 19:41 |
| deadman | really? I saw nextpnr's output with "ICESTORM_PLL: 1/2" used, and assumed I have two to play with | 19:42 |
| deadman | dang | 19:42 |
| deadman | now I gotta rethink this, and thanks for the quick answer! Been messing with this for hours | 19:43 |
| deadman | just pulled up the PLL design guide. yup, 1 pll on the cm8 package, right on the frontpage. should have picked that up. Thanks! | 19:44 |
| ross_s | no problem | 19:44 |
| ross_s | daveshah: let me know if there's any additional info you need on that routing problem. I've left it running, and its still strugging. Visiting 1459178 nodes for each arc. | 19:45 |
| daveshah | I think it's just a congested placement even though utilisation is low. I'm working on a fix for this long term but it will be a while. | 19:54 |
| daveshah | never mind, i'ts not that | 19:54 |
| daveshah | it's an occasional bug in clock placement that I need to track down | 19:55 |
| daveshah | but `wb_intercon0.wb_arbiter_spi1.wbs_ack_i_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_D_1_Z_TRELLIS_FF_DI_Q[2]` as a clock doesn't look correct to me | 19:55 |
| ross_s | hmm indeed that is not a clock | 19:55 |
| ross_s | though, since I don't have that many globals kicking about, it seems like it should be safe to route it as one without bogging down? | 19:57 |
| daveshah | yes, that's what I mean as "occasional bug in clock placement" | 19:58 |
| ross_s | ah gotcha | 19:58 |
| daveshah | it sometimes picks two global sites where the DCC inputs are shared so it isn't routeable | 19:58 |
| ross_s | is there a workaround? | 20:00 |
| daveshah | No, but in this case I think the design should be fixed | 20:01 |
| daveshah | otherwise, trying a different seed might fix it | 20:02 |
| ross_s | Hmm if something is wrong with the design I'll definitely try to fix that first | 20:02 |
| ross_s | based on the name, the suspect code would be related to this wishbone arbiter: https://github.com/olofk/wb_intercon/blob/master/rtl/verilog/wb_arbiter.v | 20:03 |
| tpb | Title: wb_intercon/wb_arbiter.v at master · olofk/wb_intercon · GitHub (at github.com) | 20:03 |
| daveshah | It looks like there might be some logic in between | 20:05 |
| daveshah | a general search for any suspicious posedges in the design should fix it | 20:05 |
| daveshah | if not I will try and fix the nextpnr issue in the next few days, but depending on the exact circumstances I wouldn't trust logic generated clocks to actually work reliably | 20:06 |
| ross_s | aha, git grep for posedge did reveal a botched @(posedge stb) that should be @(posedge clk) if (stb) ... | 20:08 |
| ross_s | rebuilding to see if that solves it | 20:08 |
| ross_s | yup, only the core clock has been promoted this time | 20:08 |
| ross_s | completed with no problems. That's an interesting gotcha, I'll be on the lookout for that if it happens again | 20:09 |
| ross_s | thanks as always for the debug help | 20:09 |
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| tnt | This seems to work: https://pastebin.com/MKGHxqYt | 20:51 |
| tpb | Title: [Diff] diff --git a/passes/cmds/ltp.cc b/passes/cmds/ltp.cc index 05701710..c9ea9eb9 10 - Pastebin.com (at pastebin.com) | 20:51 |
| tnt | nope, it doesn't. | 20:54 |
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| thardin | woohoo, the phase detector part of my lock-in amplifier is working :] | 21:57 |
| thardin | world's shittiest ADC for now | 21:57 |
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