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| sensille | is it important to do tri-stating logic only at top level? technically it shouldn't matter if the hierarchy gets flattened upfront anyway | 09:12 |
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| tnt | Does yosys have any attribute you can set to prevent it from messing / optimizing the carry chains ? | 14:08 |
| tnt | I'm guessing it tries to optimize stuff but doing so it prevents packing and so that makes things way worse and not better. | 14:09 |
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| ZirconiumX | Maybe a (* keep *)? | 14:25 |
| ZirconiumX | I mean, carry chains are whiteboxes | 14:25 |
| ZirconiumX | So only ABC9 can really "optimise" them | 14:25 |
| tnt | With abc9 the bottom lut ends up with the inputs not on the right ports for packing. Without it (so "old" abc), then the top luts end up with the input on the wrong ports for packing. | 14:26 |
| tnt | (because really it doesn't end up actually using any less luts or anything, just not using the right lut inputs for packing) | 14:27 |
| ZirconiumX | That...seems like a nextpnr thing? | 14:28 |
| tnt | nextpnr expects some specific lut input to be common to the SB_LUT4 and the SB_CARRY for them to be packable in the same LC. | 14:29 |
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| tnt | Mmm, my understanding was that it was using \$__ICE40_CARRY_WRAPPER to avoid that kind of issue. | 14:59 |
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| tnt | So the issue is the opt_lut pass | 16:50 |
| tnt | Mm ... yeah, I see the " -dlogic SB_CARRY:I0=2:I1=1:CI=0" which I assume is to prevent it from messing with I1/I2 that must stay in place for the SB_CARRY to stay there. | 17:02 |
| tnt | But there is nothing that prevents it from moving the signal coming from a SB_CARRY to I3 to somewhere else. | 17:02 |
| ZirconiumX | File a bug if you haven't already | 17:11 |
| whitequark | tnt: oh ugh I missed that | 17:12 |
| whitequark | opt_lut keeps being a PITA | 17:13 |
| tnt | I'm collecting info and trying to make the absolute minimum case. | 17:13 |
| tnt | https://github.com/YosysHQ/yosys/issues/2061 | 17:30 |
| tpb | Title: ice40: opt_lut can break carry packing by moving SB_CARRY out to another input than I3 · Issue #2061 · YosysHQ/yosys · GitHub (at github.com) | 17:30 |
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| Forty-Bot | is it possible to access module parameters from another module? | 22:17 |
| Forty-Bot | e.g. something like https://gist.github.com/Forty-Bot/d16632f50085ce708ad915a2d263a293 | 22:17 |
| tpb | Title: gist:d16632f50085ce708ad915a2d263a293 · GitHub (at gist.github.com) | 22:17 |
| ZirconiumX | No | 22:34 |
| ZirconiumX | But in your case, you don't need to | 22:35 |
| Forty-Bot | well, yeah | 22:35 |
| Forty-Bot | but the actual case I am concerned about | 22:35 |
| Forty-Bot | FOO and BAR have non-trivial formulae | 22:35 |
| ZirconiumX | Can they be computed as constant expressions? | 22:35 |
| Forty-Bot | probably? | 22:36 |
| ZirconiumX | "can you instantiate a wire that is PARAM bits wide?" | 22:36 |
| Forty-Bot | that is what I would like to do | 22:36 |
| ZirconiumX | You can use `localparam` to create a compile-time constant | 22:39 |
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