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| mwk | ohhh | 00:03 |
|---|---|---|
| mwk | okay | 00:03 |
| mwk | I see what's wrong.. | 00:03 |
| mwk | tux3: you can stop bisecting now, I understand the bug | 00:03 |
| tux3 | mwk, okay. thanks! | 00:04 |
| tux3 | I don't have a repro, but do you still want me to open an issue for it? | 00:04 |
| mwk | *sigh* fuck verilog, seriously | 00:04 |
| mwk | no, I'll take care of it | 00:04 |
| tux3 | thanks | 00:05 |
| mwk | want a quick & dirty fix that probably leaves like 100 other instances of the same problem unfixed? | 00:07 |
| tux3 | sure, why not | 00:07 |
| mwk | try out the mwk/fix-width-0 branch | 00:08 |
| mwk | (beware: it's untested) | 00:09 |
| tux3 | oh wow, that commit is a little frightening. I did not know that was necessary .... | 00:10 |
| mwk | it was not necessary before, because of a bug in verilog frontend | 00:11 |
| tux3 | ah | 00:11 |
| mwk | here's a little problem | 00:11 |
| mwk | you cannot have a 0-width wire in verilog | 00:11 |
| mwk | which is quite fucking problematic, because you can in RTLIL | 00:11 |
| tux3 | :/ | 00:11 |
| mwk | and we're using verilog for converting one cell to another, and the cell you're converting can have 0-width ports, which is *not actually expressible* in Verilog | 00:12 |
| mwk | so the input [A_WIDTH-1:0] A; line actually describes a 2-bit input | 00:12 |
| mwk | (which happen to be A[-1] and A[0]) | 00:13 |
| mwk | by passing that down to $pos, which is an internal cell that is strongly validated and expects 0-width input, you get an error | 00:13 |
| tux3 | I see | 00:14 |
| tux3 | well, your branch seems to work. Or at least, yosys gives no errors | 00:14 |
| tux3 | thanks again | 00:14 |
| mwk | alright | 00:16 |
| mwk | I'll try to get it properly fixed tomorrow | 00:16 |
| mwk | there are way more places like that | 00:17 |
| mwk | and yeah, it is a recent regression, PR #2027 specifically | 00:19 |
| mwk | tux3: your ticket is https://github.com/YosysHQ/yosys/issues/2058 | 00:31 |
| tpb | Title: Fix 0-WIDTH wire handling in techmap rules. · Issue #2058 · YosysHQ/yosys · GitHub (at github.com) | 00:31 |
| qu1j0t3 | /b 14 | 00:36 |
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| ZipCPU | mwk tux3: Is there a zero-length wire something that I need to fix in the crossbar core that I might not know about? Was it the crossbar core causing the problem? | 02:11 |
| mwk | no | 02:46 |
| mwk | there is no way it could be your issue, because you cannot actually make a zero-length wire in verilog | 02:46 |
| mwk | they appear because of yosys optimizations on RTLIL | 02:47 |
| mwk | in this case, on an $alu input | 02:47 |
| mwk | probably some const that got optimized away | 02:48 |
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| Forty-Bot | does yosys allow for some_module #(SOME_PARAMETER = foo) (/* inputs and outputs */) syntax? | 21:09 |
| daveshah | Yes | 21:10 |
| daveshah | If you mean in the module header? | 21:10 |
| Forty-Bot | I mean when instantiating the module | 21:10 |
| daveshah | No you need an instance name between the parameters and ports | 21:11 |
| Forty-Bot | ah, ok | 21:12 |
| Forty-Bot | thanks | 21:12 |
| daveshah | e.g. https://github.com/cliffordwolf/picorv32/blob/master/picosoc/icebreaker.v#L109 | 21:13 |
| tpb | Title: picorv32/icebreaker.v at master · cliffordwolf/picorv32 · GitHub (at github.com) | 21:13 |
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