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| sensille | if i had a RAM with rport and one wport, and an additional access to a fixes address (e.g. 0), would yosys be able to infer a single BRAM and duplicate write to that address to a separate register? | 15:28 |
|---|---|---|
| daveshah | No, it would see two read ports and duplicate the BRAM | 15:30 |
| sensille | ok, so i have to do that explicitly | 15:30 |
| daveshah | Yes | 15:30 |
| sensille | what does "Bram port B1 has incompatible enable structure." for TRELLIS_DPR16X4 mean? | 16:18 |
| sensille | or can i somehow find the rules myself? | 16:19 |
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| sensille | if (last_en_bit != wr_en[i + cell_port_i*mem_width]) | 16:22 |
| sensille | doesn't help me, though ;) | 16:25 |
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| sensille | at least moving the write back one cycle helped | 17:06 |
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