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| awygle | are there any good examples of throughput-based formal properties? | 04:21 |
|---|---|---|
| awygle | trying to phrase the requirement "assuming a sink which tries to read every cycle, this core's sink must be able to accept one transaction every clock cycle unless [list of exceptions]" | 04:22 |
| awygle | and i can't really figure out how to do that... | 04:22 |
| awygle | i guess i can do a cover trace fairly easily actually | 04:28 |
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| az0re | Do you have a signal for "able to accept a transaction"? | 05:35 |
| az0re | then it should be not(redor(exception_bitvector)) -> able_to_accept_transaction, no? | 05:36 |
| az0re | so "or(not(redor(exception_bitvector)), able_to_accept_transaction)" | 05:39 |
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| sensille | when yosys infers BRAM, it rejects a lot of my smallish register banks with "min efficiency 5' not met (ECP5) | 14:54 |
| sensille | is that only not to waste bram, or also that the overhead to use the bram would be similar to not using it at all? | 14:54 |
| sensille | (and others again get rejected with "Read port #0 is in clock domain !~async~.") | 15:04 |
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| ZirconiumX | sensille: it's to not waste BRAM, but there needs to be a better heuristic for it all | 15:27 |
| ZirconiumX | I think it will favour LUTRAM for it though | 15:28 |
| ZirconiumX | sensille: (and others again get rejected with "Read port #0 is in clock domain !~async~.") <--- the ECP5 has synchronous read, but you're asking for asynchronous read, for which it would use LUTRAM. | 15:30 |
| sensille | yeah, some get caught by DPR16X4 later on | 15:30 |
| sensille | i can't find the async read though, the output is explicitly registered | 15:31 |
| ZirconiumX | Generally you want BRAM for deep but narrow memories, and LUTRAM for wide but shallow memories | 15:31 |
| ZirconiumX | Can I see your Verilog module for it? | 15:32 |
| sensille | https://github.com/sensille/conan_fpga/blob/master/fifo.v | 15:33 |
| tpb | Title: conan_fpga/fifo.v at master · sensille/conan_fpga · GitHub (at github.com) | 15:33 |
| sensille | for the async read warning | 15:33 |
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| ZirconiumX | sensille: can you give the exact module path of the thing you want inferred as BRAM? | 15:56 |
| ZirconiumX | Like, conan.u_command.u_stepper.genstepdir[0].u_stepdir.u_fifo.ram | 15:56 |
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| ZirconiumX | Since as far as I can tell, the async read thing isn't actually a warning | 15:59 |
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| sensille | ZirconiumX: conan.u_framing.recv_ring for example | 16:22 |
| sensille | and conan.u_framing.send_ring | 16:23 |
| ZirconiumX | The error is actually this: Bram port B1.1 has incompatible clock type. | 16:24 |
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| ZirconiumX | By the way, you don't need to bother with `verilog -defer` if you use sensible defaults | 16:26 |
| ZirconiumX | daveshah: can you take a look at this? | 16:28 |
| daveshah | Are you initialising or resetting the output register? | 16:29 |
| ZirconiumX | Doesn't look like it | 16:30 |
| daveshah | I can have a look later | 16:31 |
| sensille | indeed, "Bram port B1.1 has incompatible clock type." is in the next line | 16:36 |
| sensille | at least my intention is that everything is driven by the one and only clk | 16:37 |
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| daveshah | With data width 8, address width 12, that file infers memory fine for me | 16:53 |
| ZirconiumX | The params used are data width 6 address width 5 | 16:54 |
| daveshah | Oh, then yes it seems to fail efficiency criterea | 16:55 |
| sensille | efficiency=22 | 16:55 |
| sensille | https://pastebin.com/vmrvT4dB | 16:56 |
| tpb | Title: Processing conan.u_framing.recv_ring: Properties: ports=2 bits=4096 rports=1 - Pastebin.com (at pastebin.com) | 16:56 |
| daveshah | Oh, not the FIFO module | 16:56 |
| sensille | it is probably how i use the fifo module | 16:56 |
| sensille | it is an instance of the fifo module | 16:57 |
| ZirconiumX | > reg [7:0] recv_ring [RING_SIZE-1:0]; | 16:57 |
| ZirconiumX | No, it's not | 16:57 |
| daveshah | That looks like an async port? | 16:58 |
| daveshah | https://github.com/sensille/conan_fpga/blob/master/framing.v#L84 | 16:58 |
| tpb | Title: conan_fpga/framing.v at master · sensille/conan_fpga · GitHub (at github.com) | 16:58 |
| * sensille blushes with shame | 17:03 | |
| sensille | ZirconiumX, daveshah: sorry, i don't know where i got the idea from it's the fifo. the fifo just fails the efficiency test | 17:04 |
| sensille | thanks for looking at this | 17:05 |
| ZirconiumX | No, I'm looking through the FIFO mappings, and it seems like all of them pass the efficiency test at 92% | 17:06 |
| daveshah | I think it would actually have mapped (as a transparent port, with the reg on the address) without the '= 0' here: https://github.com/sensille/conan_fpga/blob/master/framing.v#L83 | 17:07 |
| tpb | Title: conan_fpga/framing.v at master · sensille/conan_fpga · GitHub (at github.com) | 17:08 |
| sensille | conan.u_framing.send_len_fifo.ram fails with 1% | 17:08 |
| sensille | why is initializing the rptr a problem? | 17:10 |
| ZirconiumX | Because Yosys can't merge flops into memories at the moment | 17:10 |
| sensille | i guess i could initialize rptr with the first clk | 17:13 |
| sensille | alternatively i need to register the output? | 17:13 |
| ZirconiumX | You already have a clear option to initialise rptr | 17:16 |
| ZirconiumX | Really though, I don't know much about memories here | 17:17 |
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