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| solenskiner | Hello. I want to package the yosys suite for archlinux. I recently saw a seminar on youtube on the status for the project, and the speaker suggested to use head. Is that still true? | 09:33 |
|---|---|---|
| whitequark | the 0.9 release is quite old and there have been significant improvements in HEAD | 09:34 |
| whitequark | plus the netlists written by the 0.9 release are incompatible with nextpnr HEAD, I believe | 09:34 |
| solenskiner | I'll use head then. Thanks! | 09:35 |
| daveshah | Yes, this is one of the reasons why there hasn't been a release of nextpnr yet | 09:36 |
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| lambda | solenskiner: what exactly do you want to package? yosys is in community, yosys-git is in the AUR... | 09:50 |
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| solenskiner | Well, the whole suite, i guess: vtr, nexptr, trellis, etc. Thought that would be a good way to get familiarized with the parts, and since i'll be needing em anyways later... ¯\_(ツ)_/¯ | 10:24 |
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| daknig | maybe you wanna package symbiflow? | 10:33 |
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| solenskiner | oh, yeah, i might have confused which part was like the umbrella project? sorry | 10:37 |
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| daveshah | tbh nextpnr is more closely associated with yosys than symbiflow | 10:39 |
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| lambda | solenskiner: might want to talk to FFY00, they have a bunch of those packages already. | 10:55 |
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| ZirconiumX | The only really important bit of VTR is VPR, since there's a development effort to use it for Project X-Ray | 11:17 |
| ZirconiumX | solenskiner: ^ | 11:21 |
| ZirconiumX | And I think they use a downstream for that | 11:21 |
| daveshah | yeah, the symbiflow fork | 11:22 |
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| FFY00 | solenskiner, feel free to ping me if you need anything | 12:48 |
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| strobokopp | Hi! I'm using nmigen+yosys to generate Verilog code that I synthesize with XST from Xilinx ISE. Now there's an issue when nmigen creates a switch with cases like this: case 1'0 and case 1'- | 20:17 |
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| strobokopp | now the verilog output from yosys is casez() 1'h0 and 1'h? which XST does synthesize, but the result is wrong | 20:18 |
| whitequark | strobokopp: hi | 20:18 |
| whitequark | the verilog output from yosys looks correct to me | 20:18 |
| whitequark | does XST synthesize correctly if you take that Verilog file and use 1'h1 in it instead, keeping everything else intact? | 20:19 |
| strobokopp | whitequark: yes, then it works, I think. Let me double-check quickly.. | 20:21 |
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| strobokopp | example ilang code: https://pastebin.com/haEGUtf9 (switch \s_target is the one) | 20:22 |
| tpb | Title: module\top wire width 1 input 0 \s_target wire width 2 input 1 \s_state - Pastebin.com (at pastebin.com) | 20:22 |
| whitequark | strobokopp: actually, let's backtrack a bit. exactly which XST are you using? which device? is it one with the new parser? | 20:24 |
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| strobokopp | whitequark: alright! it's XST from ISE 14.7, not sure where to find its own version number. Device is a Spartan-3E xc3s1600e. | 20:27 |
| whitequark | are you passing `-use_new_parser yes` to XST? | 20:28 |
| strobokopp | I never heard of that parser option :) so probably no, I'll check.. | 20:28 |
| strobokopp | whitequark: I wasn't, XST warns me now that I'm on my own with this, but the netlist actually looks correct now! | 20:32 |
| whitequark | well, here you are. nmigen.build knows to pass this option automatically because otherwise xst uses a seriously noncompliant verilog parser | 20:33 |
| ZirconiumX | Oh god, I've heard bad things about ISE, but this is terrifying | 20:40 |
| strobokopp | oh well :D hours and hours of head-scratching over unexplainable behavior of the synthesized design and it's just that old parser, nmigen knew it all the time, I just didn't use it to call XST. | 20:40 |
| whitequark | good luck with whatever it is you're using a S3E for... | 20:41 |
| strobokopp | I knew I was in for trouble when I grabbed that Spartan 3 board fdrom the dumpster. | 20:41 |
| whitequark | nmigen.build currently raises a NotImplementedError for 3E, but I think we can fix that if you're willing to put in some time testing it | 20:41 |
| whitequark | I honestly thought I'll never see nmigen used for anything older than 3A | 20:41 |
| whitequark | what's next, virtex-2? : | 20:41 |
| whitequark | *:D | 20:41 |
| strobokopp | hey you never know what you'll find in the junk, don't be suprised if I do show up again with sometrhing ancient! | 20:43 |
| daveshah | xc2064 is where it is at! | 20:43 |
| strobokopp | whitequark: but I could sure do some tests with the Spartan-3E to have support for it in nimgen | 20:44 |
| ZirconiumX | I mean, we accidentally added support for the wrong Cyclone chip, WQ. I'm honestly surprised they're still fucking making EP3C | 20:44 |
| whitequark | lol | 20:45 |
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| daveshah | Big vendor FPGAs have pretty good longevity | 20:47 |
| daveshah | I think Xilinx promise 20 years or something of that magnitude | 20:48 |
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| daveshah | Heck, looks like Spartan 2 are still available to buy on DigiKey and not even flagged as obsolete | 20:51 |
| whitequark | wow | 20:51 |
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| ZirconiumX | The manual for the EP3C has a 1.0 release of March 2007. | 21:12 |
| ZirconiumX | So yeah | 21:12 |
| daveshah | Cyclone III is a bit special given that the arch lives on in a strange way | 21:14 |
| daveshah | I think Cyclone IVE is pretty much a direct die shrink of it | 21:14 |
| daveshah | and then that became 10LP | 21:15 |
| strobokopp | ah and I'm pleased to see that there is also plenty of Spartan-3E supply on digikey. Virtex-II seems to be harder to find, having been discontinued in 2012 already! They really let us down there. | 21:19 |
| strobokopp | oh wait, some Virtex-II Pro were only discontinued in 2018 | 21:21 |
| strobokopp | and then the rest (?) in February 2020 | 21:22 |
| daveshah | Still time for a last time buy! | 21:26 |
| daveshah | https://www.digikey.co.uk/product-detail/en/xilinx-inc/XC2VP70-7FF1517C/XC2VP70-7FF1517C-ND/6132147 | 21:26 |
| tpb | Title: XC2VP70-7FF1517C Xilinx Inc. | Integrated Circuits (ICs) | DigiKey (at www.digikey.co.uk) | 21:26 |
| daveshah | Subject to mortgage approval at that price though | 21:26 |
| strobokopp | needs better justification than trying to fix an old dev board to toy around with | 21:28 |
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| strobokopp | whitequark: thanks, by the way. I don't think I would've had the will to look any further myself. I would've just blamed ISE and written a script to replace the question marks :D | 21:42 |
| strobokopp | now I can still blame ISE, but in a somewhat educated manner | 21:43 |
| whitequark | no problem, glad i could help | 21:50 |
| whitequark | (don't tell anyone, but: i don't even use ISE. i just googled `"ISE" "casez" bug` and found a Xilinx AR recommending the option) | 21:51 |
| strobokopp | smart! | 22:06 |
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