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| tux3 | Has anyone thought about rewriting the verilog frontend? | 01:25 |
|---|---|---|
| tux3 | Every time I try to improve something and end up in simplify.cc, it makes me want to install <proprietary tool> :/ | 01:25 |
| awygle | I am sure many people have _thought_ about it lol | 01:37 |
| whitequark | i believe rewriting the verilog frontend is very much encouraged | 01:45 |
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| bubble_buster | is verilator's frontend any good? it occurred to me a while ago that verilator has pretty complete synthesizable SV support, and it essentially "synthesizing" the input RTL, I wonder why that hasn't been mapped to yosys? licensing? or is it not as straightforward as I imagine? | 03:42 |
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| awygle | verilator is AL/GPL both of which are copyleft so i imagine that's an issue | 04:11 |
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| awygle | but also, probably it's not straightforward | 04:11 |
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| lambda | weird, -Wextra is supposed to enable -Wimplicit-fallthrough=3, which allows comments like "falls through" to silence the warning: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html but the travis builds with g++9 report them anyway: https://travis-ci.org/github/YosysHQ/yosys/jobs/682632651#L661 | 16:42 |
| tpb | Title: Warning Options (Using the GNU Compiler Collection (GCC)) (at gcc.gnu.org) | 16:42 |
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| ZirconiumX | Unnecessary bikeshedding: Yosys is capitalised, but nextpnr is not, right? | 18:05 |
| daveshah | Yes | 18:05 |
| ZirconiumX | When did the JSON format change for nextpnr? I'm writing a mini-cookbook for Yosys etc and I think the format broke at some point | 18:14 |
| ZirconiumX | So I want to give a rough date for "your stuff is too old" | 18:15 |
| ZirconiumX | Since "master" or "latest" are not really valid versions :P | 18:15 |
| daveshah | I think the last change to affect ice40/ecp5 was around August 2019? | 18:25 |
| ZirconiumX | So 0.9? | 18:27 |
| ZirconiumX | Ish | 18:28 |
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| awygle | daveshah: are you open to taking something besides the JSON RTLIL representation as input to nextpnr? (ref. some discussions yesterday about RTLIL instability and LoFIRRTL) | 18:30 |
| daveshah | Post 0 | 18:30 |
| daveshah | Post 0.9 release | 18:31 |
| awygle | (assuming somebody did the work, which, yknow, we're all busy lol) | 18:31 |
| daveshah | awygle: sure, although note that JSON is somewhat different to RTLIL | 18:31 |
| daveshah | But adding a new format shouldn't be too hard | 18:31 |
| awygle | oh? i thought it was just a representation of the RTLIL | 18:31 |
| daveshah | It is, but it is in a way that reduces the things that have compatability problems | 18:32 |
| awygle | (not to be confused with ilang, which iiuc is the [a] text representation of RTLIL) | 18:32 |
| daveshah | In particular it doesn't support processes | 18:32 |
| daveshah | The JSON spec also says new fields can be added and anything parsing has to ignore them | 18:32 |
| awygle | that's nice | 18:32 |
| daveshah | Although it has broken in the past, it should be pretty stable now | 18:32 |
| daveshah | That was due to a change in the way parameters are encoded | 18:33 |
| ZirconiumX | I'm wondering if `synth_ice40 -retime` should be recommended or not. | 18:34 |
| ZirconiumX | (currently I suggest `-dsp` for ultraplus) | 18:34 |
| daveshah | Definitely not, the current retiming is pretty horrible | 18:34 |
| daveshah | Its been rare to see a QoR improvement and it makes debugging harder if registers are messed with | 18:35 |
| ZirconiumX | Basically, I have four categories of options that aren't "default": useful (-top and -noflatten), sometimes useful (-dffe_min_ce_use if there's routing congestion, maybe?), worth mentioning (ABC9 for iCE40 might get better with time), and not worth mentioning (does anybody even use -nocarry?) | 18:38 |
| daveshah | nocarry is mostly useful if you think there is a bug related to carry chains | 18:39 |
| ZirconiumX | Or -nobram | 18:39 |
| daveshah | Ditto | 18:40 |
| daveshah | But not so much for ice40 where it will likely explode the design | 18:40 |
| daveshah | But for ECP5 I've forced everything into lutram to make sure a bug wasn't bram related | 18:40 |
| ZirconiumX | Sure, but if I'm mostly targeting somebody asking "what do these levers do?", I don't think it's important to mention them | 18:40 |
| daveshah | No | 18:40 |
| daveshah | Indeed not | 18:41 |
| awygle | 2c, i'd want you to mention them and say "these are for debugging, not for production use, here's what they do", because otherwise i'd be like "hey wait these show up in -help but you don't mention them! is this article out of date?!" | 18:41 |
| awygle | but i may be atypical | 18:42 |
| ZirconiumX | Okay, valid point | 18:42 |
| awygle | btw why does yosys use single - instead of double -- ? this always annoys me when i encounter it :( | 18:43 |
| ZirconiumX | Conversely it always annoys me when I have to use -- for nextpnr :P | 18:44 |
| whitequark | yosys passes aren't unixy tools | 18:44 |
| whitequark | i guess that's why | 18:44 |
| daveshah | Vivado tcl commands, for example use single dash too, iirc | 18:46 |
| ZirconiumX | Likewise for Quartus I think | 18:49 |
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| ZirconiumX | Is -edif for icecube or something? | 19:00 |
| ZirconiumX | (in synth_ice40) | 19:00 |
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| ZirconiumX | daveshah: ^ | 19:01 |
| daknig | what's the status of yosys regarding to the support of the 7 series? what features are missing? | 19:02 |
| daknig | I am new to FPGAs and I was thinking of using yosys for my project , but it requires the DDR memory on my zynq and DSP slices (as well as other things) | 19:03 |
| ZirconiumX | I think shift-register inference is not quite there yet | 19:03 |
| ZirconiumX | DSP48E1 is supported AIUI | 19:03 |
| ZirconiumX | And can be inferred | 19:03 |
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| jfierro | Hi all. Not sure how useful this could be to this group but here's a diagram of the Xilinx 7-Series SLICEL architecture that I made: https://raw.githubusercontent.com/jfierro/fpga-doc/master/xilinx/7-Series_SLICEL.svg. | 19:08 |
| ZirconiumX | jfierro: Maybe it's more useful in #symbiflow? | 19:09 |
| jfierro | As far as I know they already know what they need about the SLICEL, but yeah you're right :) | 19:12 |
| ZirconiumX | Generally this stuff is too low-level for Yosys | 19:13 |
| ZirconiumX | But it's useful anyway | 19:13 |
| * ZirconiumX stares at the lack of documentation they have for Intel chips | 19:13 | |
| ZirconiumX | Well, I mean, I made a diagram for the ALM | 19:16 |
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| ZirconiumX | Also, thinking about it, -nocarry can sometimes be faster due to it using Brent-Kung instead of ripple-carry, right? | 19:43 |
| ZirconiumX | *faster than carry chains | 19:43 |
| daveshah | Given that the carry chains are so much faster than fabric, I've never seen an Fmax improvement with -nocarry | 19:44 |
| ZirconiumX | Mmm, fair. | 19:44 |
| ZirconiumX | -nodffe *may* reduce routing congestion, right? | 19:46 |
| daveshah | Yes, definitely | 19:47 |
| ZirconiumX | Because it doesn't have to route the enable signal | 19:47 |
| daveshah | Sometimes there are optimisations possible without the enable too | 19:48 |
| daveshah | And it makes placement easier by reducing the number of control sets | 19:48 |
| daveshah | But dffe_min_ce_use is less of a blunt instrument than nodffe | 19:48 |
| ZirconiumX | https://gist.github.com/ZirconiumX/a64c38741c4ec8b907b1f2fabe675af4 <-- thoughts? also from awygle | 19:52 |
| tpb | Title: ice40.md ยท GitHub (at gist.github.com) | 19:52 |
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| daveshah | Looks good! | 20:04 |
| awygle | looks good to me too though i'm _definitely_ not who you want to be asking :p | 20:09 |
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