| *** tpb has joined #yosys | 00:00 | |
| *** jjjaaaccckkk has joined #yosys | 00:08 | |
| *** vidbina_ has quit IRC | 00:23 | |
| *** lutsabound has quit IRC | 03:34 | |
| *** jjjaaaccckkk has quit IRC | 04:02 | |
| *** jjjaaaccckkk has joined #yosys | 04:09 | |
| *** rohitksingh has joined #yosys | 05:49 | |
| *** emeb_mac has quit IRC | 06:57 | |
| *** rohitksingh has quit IRC | 07:02 | |
| *** dys has quit IRC | 07:57 | |
| *** svenn has quit IRC | 08:09 | |
| *** svenn has joined #yosys | 08:09 | |
| *** jakobwenzel has joined #yosys | 08:09 | |
| rjo | i didn't see anything in the logs. maybe about fabric clock enables but not about the SB_IO | 08:31 |
|---|---|---|
| rjo | daveshah: got a link? | 08:31 |
| rjo | or alternatively: does https://github.com/YosysHQ/yosys/blob/58ab9f6021bc5b90956d97759ef0f3bc8c7e209e/techlibs/ice40/cells_sim.v#L1387-L1399 match reality? | 08:32 |
| tpb | Title: yosys/cells_sim.v at 58ab9f6021bc5b90956d97759ef0f3bc8c7e209e · YosysHQ/yosys · GitHub (at github.com) | 08:32 |
| daveshah | rjo: see https://twitter.com/whitequark/status/1117916690547789824 (thread) | 08:34 |
| *** citypw has joined #yosys | 08:34 | |
| rjo | that ends with questions... | 08:36 |
| daveshah | rjo: sorry, meant to link this one | 08:38 |
| daveshah | https://twitter.com/whitequark/status/1117917683859673088 | 08:38 |
| daveshah | The Yosys sim model should be correct | 08:38 |
| rjo | ok. thanks! | 08:39 |
| *** dys has joined #yosys | 08:54 | |
| *** thasti has joined #yosys | 10:39 | |
| *** citypw has quit IRC | 11:05 | |
| *** citypw has joined #yosys | 11:05 | |
| *** citypw has quit IRC | 11:09 | |
| *** citypw has joined #yosys | 11:10 | |
| *** fsasm has joined #yosys | 11:27 | |
| heijligen | Hi, what does yosys mean by "Executing EDIF backend. ERROR: Don't know how to handle 1'z on (portRef (member gp0_out 0))." | 11:33 |
| az0re | looks like you have some tri-state buffer it doesn't like | 11:37 |
| *** citypw has quit IRC | 11:38 | |
| az0re | (just a guess; I'm not familiar with the EDIF backend at all) | 11:39 |
| mwk | heijligen: what target is it? in general, 1'bz shouldn't survive until EDIF | 11:45 |
| heijligen | my input are +/xilinx/cells/xtra.v and vhdl through ghdl | 11:46 |
| heijligen | yosys -m ghdl -p "read_verilog +/xilinx/cells_xtra.v; ghdl --std=08 $^ -e top; synth_xilinx -top top -edif $@" | 11:47 |
| heijligen | I'm trying to wrap the PS7 primitives into vhdl records | 11:48 |
| heijligen | mwk: it's an Zynq7020 | 11:49 |
| mwk | heijligen: are you using the latest git yosys? there have been a lot of improvements to tristate support recently | 11:53 |
| mwk | also, why are you manually adding cells_xtra.v? synth_xilinx should do it on its own | 11:53 |
| heijligen | I'm using Yosys 0.9+932 (git sha1 8b2c9f45, gcc 8.3.1 -fPIC -Os), will rebuild and test with git master | 11:54 |
| mwk | wait a moment | 11:55 |
| heijligen | ok, that synth_xilinx is including the rechlibs wasn't known to me | 11:55 |
| mwk | okay, you should still update | 11:55 |
| mwk | but | 11:55 |
| mwk | that seems to be new enough that tristate buffer is in, just not enabled by default | 11:56 |
| mwk | try adding -iopad to synth_xilinx | 11:56 |
| daveshah | I don't know if cells_xtra being read by synth_xilinx works here, if ghdl needs the blackboxes | 11:56 |
| daveshah | (as synth_xilinx is after ghdl) | 11:56 |
| *** Stary has quit IRC | 11:59 | |
| mwk | hmm, true, dunno about ghdl | 12:01 |
| heijligen | I'll rebuild the toolchain and run it again | 12:02 |
| heijligen | I've no inout wires in my design, so why should there something with a tri-state buffer | 12:03 |
| heijligen | my code is at https://github.com/heijligen/vhdl_pynq, it's a simple blink example | 12:04 |
| heijligen | blink is working, blink2 not | 12:04 |
| *** Stary has joined #yosys | 12:04 | |
| *** vidbina_ has joined #yosys | 12:18 | |
| mwk | heijligen: could you run synth_xilinx without edif output, use `dump` to write the ilang file afterwards, then upload it somewhere? | 12:37 |
| mwk | could be a missing wire somewhere | 12:37 |
| heijligen | mwk: https://gist.github.com/heijligen/ff7a64b1f559de43a2509d503b99edb2 | 13:09 |
| tpb | Title: blink2.dump · GitHub (at gist.github.com) | 13:10 |
| heijligen | the error by synth_xilinx -edif is ERROR: Don't know how to handle 1'z on (portRef (member gp0_out 106)). | 13:10 |
| mwk | heijligen: uhh, this dump doesn't appear to even contain your module? | 13:15 |
| heijligen | when i say "show top" the output is correct | 13:18 |
| mwk | what about "dump top"? | 13:21 |
| heijligen | I've updated the gist. there is mow a top | 13:25 |
| heijligen | mwk: https://pasteboard.co/IPMqw4F.png | 13:31 |
| tpb | Title: Pasteboard - Uploaded Image (at pasteboard.co) | 13:31 |
| mwk | alright, so it seems that zynq_ps7 does something stupid | 13:40 |
| mwk | gp0_out is connected to 'z | 13:40 |
| mwk | or at least bits [77:66] of it | 13:40 |
| heijligen | most of zynq_ps7 is not connected. I don't need it yes and leave the ports open | 13:44 |
| mwk | it's about zynq_ps7 driving a 'z on some of *its* output ports | 13:46 |
| heijligen | what does 'z mean? I'm relative new to this stuff | 13:48 |
| mwk | hmm. | 13:49 |
| mwk | well, 'z means unconnected | 13:49 |
| mwk | ie. you're not assigning a value to some of the output ports | 13:49 |
| mwk | well, undriven really, not unconnected | 13:49 |
| mwk | you know what, I'll cook you a patch | 13:49 |
| heijligen | ok, that is wat I wanted. this wires are there from the verilog module and i've wrapped them in vhdl and do not need them | 13:50 |
| mwk | heijligen: try out mwk/edif-z branch of yosys | 13:52 |
| mwk | I think it should be the correct fix | 13:52 |
| heijligen | It's building successfully | 14:00 |
| heijligen | mwk: the bitstream is working. thanks | 14:10 |
| *** DurandA59 has joined #yosys | 14:25 | |
| DurandA59 | Hi everyone. I have a quick question concerning Yosys: what are BUFs that are drawn everywhere from my design using the show command. | 14:37 |
| ZirconiumX | Buffers | 14:39 |
| daveshah | They are used for aliases between net names | 14:40 |
| ZirconiumX | What are you targeting? | 14:40 |
| daveshah | They aren't really cells in the netlist | 14:40 |
| DurandA59 | I am targetting ECP5 using Trellis. So this is just for the xdot representation and doesn't map to an actual element of the FPGA? | 14:43 |
| daveshah | No, they don't have any relationship to FPGA mapping | 14:43 |
| daveshah | They are really just giving an alternative name to a net, equivalent to "assign b = a;" in Verilog | 14:44 |
| DurandA59 | Thank you very much! | 14:45 |
| *** DurandA59 has quit IRC | 14:51 | |
| *** develonepi3 has joined #yosys | 15:35 | |
| *** vidbina_ has quit IRC | 15:42 | |
| *** vidbina_ has joined #yosys | 15:44 | |
| *** emeb has joined #yosys | 15:51 | |
| *** az0re has quit IRC | 16:32 | |
| *** vidbina_ has quit IRC | 17:19 | |
| *** Stary has quit IRC | 18:09 | |
| *** Stary has joined #yosys | 18:11 | |
| *** dys has quit IRC | 18:22 | |
| *** Jybz has joined #yosys | 18:39 | |
| *** Jybz has quit IRC | 18:56 | |
| *** Jybz has joined #yosys | 18:57 | |
| *** X-Scale` has joined #yosys | 19:32 | |
| *** X-Scale has quit IRC | 19:34 | |
| *** X-Scale` is now known as X-Scale | 19:34 | |
| *** vidbina_ has joined #yosys | 19:35 | |
| *** Laksen has joined #yosys | 19:52 | |
| *** dh73 has joined #yosys | 19:57 | |
| *** vidbina_ has quit IRC | 20:00 | |
| *** az0re has joined #yosys | 20:02 | |
| *** fsasm has quit IRC | 20:05 | |
| *** X-Scale has quit IRC | 20:37 | |
| *** X-Scale` has joined #yosys | 20:37 | |
| *** X-Scale` is now known as X-Scale | 20:38 | |
| *** Jybz has quit IRC | 20:43 | |
| *** az0re has quit IRC | 20:46 | |
| *** emeb_mac has joined #yosys | 20:49 | |
| *** adjtm_ has quit IRC | 21:01 | |
| *** adjtm has joined #yosys | 21:01 | |
| *** az0re has joined #yosys | 21:08 | |
| *** fsasm has joined #yosys | 21:14 | |
| *** fsasm has quit IRC | 21:41 | |
| *** TheHolyC has quit IRC | 21:52 | |
| *** TheHolyC has joined #yosys | 21:52 | |
| *** elfGamal has joined #yosys | 21:58 | |
| *** elGamal has quit IRC | 21:59 | |
| *** vidbina_ has joined #yosys | 22:07 | |
| *** Laksen has quit IRC | 23:05 | |
| *** vidbina_ has quit IRC | 23:15 | |
| *** adjtm has quit IRC | 23:41 | |
| *** adjtm has joined #yosys | 23:41 | |
| *** az0re has quit IRC | 23:50 | |
| *** dh73 has quit IRC | 23:58 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!
