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| jjjaaaccckkk | Or anyone know Mathias and can ask if he is open to sharing them? | 02:31 |
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| az0re | No, unfortunately, I've never met him. But it sounds like Clifford knows him reasonably well. Maybe you can ask him to ask Mathias to post them publicly/more prominently? | 08:42 |
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| plaes | jjjaaaccckkk: there's prjxray for xilinx7 | 10:27 |
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| ZirconiumX | daveshah: Is there a way to get nextpnr to output longest combinational path in out-of-context mode? | 13:57 |
| daveshah | I don't know | 13:57 |
| daveshah | The current timing analysis code is a bit crap | 13:57 |
| daveshah | You could always just wrap you combinational logic in two registers | 13:58 |
| daveshah | That should make it actually optimise for timing too | 13:58 |
| ZirconiumX | Ah, yes, that works, thank you | 14:07 |
| ZirconiumX | Unfortunately the critical path report is...unhelpful. | 14:07 |
| daveshah | I suspect the problem is more abc than anything nextpnr | 14:09 |
| ZirconiumX | autoname at least is giving very painful names | 14:09 |
| ZirconiumX | Source \$4560_LUT4_Z_53_A_LUT4_Z_D_LUT4_Z_B_LUT4_Z_D_LUT4_C_Z_LUT4_D_B_LUT4_Z_SLICE.F1 | 14:10 |
| ZirconiumX | ERROR: Assert `existing_cell' failed in passes/techmap/abc9.cc:510 | 14:11 |
| ZirconiumX | Oh goody. | 14:11 |
| daveshah | I think there were some changes to abc9 recently, they may well have broken something | 14:14 |
| ZirconiumX | Bugpointing | 14:16 |
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| rjo | on iCE40, SB_IO, from the silicon blue schematics: if CLOCK_ENABLE goes high while the clock is already high, that would create a spurious late clock edge for the FFs in the SB_IO. I.e. That spurious clock edge could easily violate timing. Is that correct? | 22:22 |
| daveshah | This was discussed a few months ago | 22:24 |
| whitequark | rjo: the siliconblue schematics for SB_IO are blatantly wrong | 22:24 |
| daveshah | The conclusion was the diagram is wrong | 22:24 |
| daveshah | Yup | 22:24 |
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| whitequark | it does not match common sense or silicon behavior | 22:24 |
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