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| lukego | daveshah: thanks for the twitter thread link | 11:34 |
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| FSM_Dude | Hello! | 11:57 |
| ZirconiumX | Hiya | 11:58 |
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| FSM_Dude | I just synthesised a design and written it back to a verilog file using Yosys' `write_verilog` function. In the generated verilog file I see the selected cells from the cell library I used. | 12:02 |
| FSM_Dude | Would it be possible for me to create new cell with the same input and output as the selected cells, and then replace the selected cell with my new cell? | 12:03 |
| ZirconiumX | FSM_Dude: Depending on your requirements, techmap could do that | 12:08 |
| FSM_Dude | Okay, Ive written a TMR Flip Flop design in verilog. I'd like to synthesise that, and replace all Flip Flops in another design by those TMR Flip Flops | 12:09 |
| ZirconiumX | FSM_Dude: ...why did you have to bring up flip-flops? | 12:13 |
| ZirconiumX | They are amongst the most painful parts of Yosys at the moment | 12:13 |
| FSM_Dude | Im interested in the differences between using normal flips-flops vs TMR flip-flops | 12:14 |
| ZirconiumX | But yeah, you'd use techmap | 12:14 |
| FSM_Dude | Cool, Im gonna read some about `techmap` | 12:14 |
| FSM_Dude | Thanks a lot! | 12:14 |
| ZirconiumX | You'll want to use Yosys' internal documentation rather than the stuff on Clifford's website, as it's generally more up to date | 12:15 |
| FSM_Dude | Okay, I'll build the documentation then:) thanks again! | 12:17 |
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| FSM_Dude | `(* techmap_simplemap *)(* techmap_celltype = "$sr $ff $dff $dffe $adff $dffsr $dlatch" *)module _90_simplemap_registers;endmodule` | 13:24 |
| FSM_Dude | woops* | 13:24 |
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| pepijndevos | It seems that Yosys does not have a remainder operator, as present in VHDL. How does this work in Verific? | 16:16 |
| pepijndevos | Is that something that could be added? | 16:16 |
| whitequark | you probably want a new cell | 16:16 |
| whitequark | i imagine you want a new cell for division too | 16:16 |
| whitequark | (I assume VHDL uses quo/rem, in contrast to Verilog's div/mod) | 16:17 |
| pepijndevos | Why division? Are $div semantics diffrent than VHDL division? | 16:17 |
| pepijndevos | VHDL has both mod and rem operators | 16:18 |
| whitequark | hm | 16:18 |
| whitequark | try dividing by a negative number in both verilog and vhdl and compare the result | 16:18 |
| pepijndevos | I would not be surprised if Verilog is one of those cursed languages that has only modulus that is actually remainder but is still called modulus. | 16:20 |
| whitequark | hang on, i had a handy table somewhere | 16:20 |
| whitequark | hm | 16:21 |
| whitequark | https://en.wikipedia.org/wiki/Modulo_operation#In_programming_languages | 16:22 |
| tpb | Title: Modulo operation - Wikipedia (at en.wikipedia.org) | 16:22 |
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| whitequark | pepijndevos: yeah so I think the $mod cell in Yosys actually corresponds to the rem operation in VHDL | 16:23 |
| pepijndevos | Yea, just what I thought... | 16:24 |
| pepijndevos | *facepalm* | 16:24 |
| whitequark | it... should be renamed I think | 16:24 |
| pepijndevos | It'd be great if we could stop propagating C errors | 16:24 |
| whitequark | anyway, this is why nmigen actually prohibits signed division/modulo operations | 16:24 |
| whitequark | python's % also has the remainder semantics | 16:25 |
| whitequark | and it's also called __mod__ of course | 16:25 |
| pepijndevos | *prohibits* haha | 16:26 |
| whitequark | that lets me avoid adding new yosys cells | 16:28 |
| pepijndevos | should I make a yosys issue for this? | 16:31 |
| pepijndevos | Too late to prohibit signed modulus in VHDL now ;) | 16:31 |
| whitequark | an issue, sure, but I expect that if you want this cell you'll have to implement it yourself | 16:36 |
| pepijndevos | Probably... and I don't think I care about signed modulus enough to do this. I guess GHDL will just throw an error... | 16:38 |
| pepijndevos | I'm going to try and see what verific does... | 16:40 |
| emily | +1 to not propagating C errors | 16:40 |
| emily | the worst part is that it means hardware implements the mathematically less useful one | 16:40 |
| emily | because of C | 16:40 |
| whitequark | integer or floating-point | 16:42 |
| pepijndevos | DOHHH!! Verific does the wrong thing and just makes a $mod cell for both mod and rem | 16:47 |
| emily | whitequark: I forget, but I think integer at least | 16:48 |
| emily | pepijndevos: :((((( | 16:48 |
| whitequark | lol | 16:49 |
| daveshah | I suspect this is a bug in the Yosys Verific integration | 16:51 |
| daveshah | https://github.com/YosysHQ/yosys/blob/master/frontends/verific/verific.cc#L484 | 16:52 |
| tpb | Title: yosys/verific.cc at master · YosysHQ/yosys · GitHub (at github.com) | 16:52 |
| pepijndevos | yep | 16:59 |
| emily | so much for "verif" | 16:59 |
| pepijndevos | Well, to be fair, can't blame verific in this case. | 17:02 |
| pepijndevos | https://github.com/YosysHQ/yosys/issues/1523 | 17:09 |
| tpb | Title: Yosys modulus operator has remainder semantics · Issue #1523 · YosysHQ/yosys · GitHub (at github.com) | 17:09 |
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| pepijndevos | whelp, I didn't actually remember which way Python % works... apparently *not* the same as verilog | 17:22 |
| whitequark | er, i'm wrong | 17:23 |
| whitequark | python's % is actually modulo | 17:23 |
| whitequark | the issue with division was something else, um | 17:23 |
| pepijndevos | Verilog % is sign of dividend, Python % is sign of divisor | 17:24 |
| pepijndevos | Yea, so python is modulo, verilog is remainder | 17:24 |
| whitequark | the sign of the result of division in python is xor of the signs of operands | 17:25 |
| pepijndevos | That's just... how math works, no? | 17:28 |
| whitequark | yes | 17:28 |
| whitequark | so i'm trying to remember where it doesn't match verilog | 17:28 |
| whitequark | there was something but i forgot :( | 17:29 |
| pepijndevos | divide by zero? | 17:29 |
| whitequark | no, nmigen defines that, so i emit a mux | 17:29 |
| whitequark | (x/0=0) | 17:29 |
| * pepijndevos screams in math | 17:30 | |
| whitequark | you'll be delighted that coq also defines division by zero to return zero | 17:30 |
| whitequark | and you can't really argue that it wasn't written by, well, mathematicians | 17:31 |
| whitequark | *to learn that | 17:31 |
| whitequark | for the same reasons too: it would be silly to return an Option<T> in that case, and using an exception wouldn't be good too, and you have perfectly good formal verification tools right in your toolkit | 17:32 |
| whitequark | oh of course | 17:32 |
| whitequark | Python division truncates towards -inf, Verilog division truncates towards zero | 17:32 |
| pepijndevos | ah yea i was about to suggest that | 17:32 |
| whitequark | which one does Verilog have? | 17:33 |
| whitequark | er | 17:33 |
| whitequark | VHDL | 17:33 |
| pepijndevos | I'm scared to look | 17:33 |
| pepijndevos | Probably the one Verilog doesn't have, leading to another bug | 17:33 |
| ZirconiumX | I just dragged out the VHDL 2008 spec | 17:35 |
| ZirconiumX | I can't into maths, so I'm hoping somebody can recognise it | 17:35 |
| ZirconiumX | IEEEStd 1076-2008IEEE STANDARD VHDL LANGUAGE REFERENCE MANUAL128Copyright © 2009 IEEE. All rights reserved.Integer division and remainder are defined by the following relation:A = (A/B) * B + (A rem B) | 17:35 |
| ZirconiumX | ...Thanks | 17:35 |
| whitequark | do you have a link to the pdf? | 17:36 |
| ZirconiumX | https://pastebin.com/7GFEvCmt | 17:37 |
| tpb | Title: Integer division and remainder are defined by the following relation: A = (A - Pastebin.com (at pastebin.com) | 17:37 |
| pepijndevos | So how do you hanldle division by negative numbers in nMigen | 17:37 |
| ZirconiumX | whitequark: ftp://ftp.lpp.polytechnique.fr/jeandet/keep/sync/vhdl/4772740_IEEE-1076_Standard-VHDL-Language-Ref-Manual.pdf | 17:38 |
| whitequark | pepijndevos: it is a compile time error to use a signed number on the right hand side of % or // operator | 17:38 |
| pepijndevos | I see | 17:38 |
| whitequark | sometimes, the best way to deal with a hard problem is avoidance :) | 17:38 |
| OK_b00m3r | :) | 17:39 |
| pepijndevos | So only division by a constant? | 17:39 |
| OK_b00m3r | whitequark: may i OH that | 17:39 |
| OK_b00m3r | with ur nick | 17:39 |
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| whitequark | I guess? | 17:40 |
| whitequark | pepijndevos: no. nmigen has signed and unsigned values, which are separate types | 17:40 |
| pepijndevos | ah ofc | 17:40 |
| whitequark | (all values in nmigen have integer type with two properties: width and signedness) | 17:40 |
| pepijndevos | Okay, I think... VHDL does it the Verilog way, and round to zero | 17:48 |
| pepijndevos | ah wait... | 17:48 |
| pepijndevos | so confusing for my sleepy brain | 17:48 |
| pepijndevos | At least I'm pretty sure that equation ZirconiumX posted does not hold in Python | 17:51 |
| pepijndevos | Therefore I assume VHDL does the right thing (for DSP quantization error) and round to zero. | 17:52 |
| pepijndevos | Or not... | 17:52 |
| pepijndevos | Actually... well, never mind... | 17:53 |
| whitequark | hm, let's say A=-10, B=3, A rem B=-1, -10=(A/B)*3-1, A/B=-3 | 17:53 |
| whitequark | that seems to imply round towards zero | 17:53 |
| pepijndevos | hurray | 17:54 |
| pepijndevos | Still thinking about the DSP part... I remember that some ADC designer truncated LSB rather than rounding properly, creating some horrible cross-over distortion. But I'm not awake enough to figure out which division scheme would be worse. | 17:56 |
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